MPC8540 datasheet(1075/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

18-27

18.5.1.8 Interrupts and Power Management

Whether low-power modes are automatically re-enabled after an interrupt is processed differs

depending on whether the low power mode was entered due to a write to the core MSR[WE] bit

or the low power mode was entered due to a write to POWMGTCSR.

18.5.1.8.1 Interrupts and Power Management Controlled by MSR[WE]

When an interrupt is asserted to the CPU, the core complex saves portions of the MSR to

MCSRR1, CSRR1, or SRR1 (depending on the type of interrupt), and restores those values on

return from the routine. MSR[WE], which gates the doze, nap, and sleep power management

outputs (internal device signals) from the core complex, is always among the bits saved and

restored; hence these outputs negate to the MPC8540 power management logic when the interrupt

begins processing in the core. They return to their previous state when the core executes an rfi,

rfci, or rfmci instruction. Section 10.1.3, “Interrupts to the Processor Core,” lists interrupts that

cause the MPC8540 to wake up.

NOTE

Returning doze, nap, and sleep signals to their original state when

MSR[WE] is restored differs from how power management is

implemented on earlier PowerPC devices where MSR[POW], which

enables power-down requests, is cleared when the processor exits a

low-power state and is not automatically restored, as it is in Book E

implementations.

18.5.1.8.2 Interrupts and Power Management Controlled by POWMGTCSR

The IRQ_MSK and CI_MSK fields of the POWMGTCSR register prevent int interrupts or cint

critical interrupts from waking the device from a low power state. This is true regardless of the

method used to enter the low power state.

Any unmasked interrupt (not masked by the mask bits in the POWMGTCSR register) causes the

POWMGTCSR[DOZ,SLP] fields to be cleared when it occurs. When such an interrupt occurs, the

device returns to the normal operating mode and does not automatically attempt to return to a low

power state after the interrupt is handled.

Note that interrupts caused by the unconditional debug event (UDE) and machine check (MCP)

signals are not masked by the IRQ_MSK and CI_MSK fields; therefore, when these signals assert,

the POWMGTCSR[DOZ,SLP] fields are cleared and the device will return to full power

operation. See Section 18.4.1.12, “Power Management Control and Status Register

(POWMGTCSR),” for detailed information about the bits of POWMGTCSR.

MPC8540 Datasheet(PDF) 1075 Page - Freescale Semiconductor, Inc