MPC8540 datasheet(1094/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

19-16

Freescale Semiconductor

Performance Monitor

DDR Memory Controller Events

Cycles a read is returning data from

DDR SDRAM

Ref:10

Each data beat returned to the memory controller on the

DDR SDRAM interface

Cycles a read or write transfers data

from (or to) DDR SDRAM

Ref:11

Each data beat transferred to or from the DDR SDRAM

Pipelined read misses in the row open

table

C1:57

Row open table read misses issued while a read is

outstanding

Pipelined read or write misses in the

row open table

C2:0

Row open table read or write misses issued while a read or

write is outstanding

Non-pipelined read misses in the row

open table

C3:60

Row open table read misses issued when no reads are

outstanding

Non-pipelined read or write misses in

the row open table

C4:0

Row open table read or write misses issued when no reads

or writes are outstanding

Pipelined read hits in the row open

table

C5:56

Row open table read hits issued when a read is outstanding

Pipelined read or write hits in the row

open table

C6:0

Row open table read or write hits issued when a read or

write is outstanding

Non-pipelined read hits in the row open

table

C7:57

Row open table read hits issued when no reads are

outstanding

Non-pipelined read or write hits in the

row open table

C8:0

Row open table read or write hits issued when no reads or

writes are outstanding

Forced page closings not caused by a

refresh

C1:0

Precharges issued to the DDR SDRAM for any reason

except refresh. The possibilities are as follows:

• A new transaction must be issued to an already active

bank and sub-bank that has a different row open.

• A new transaction must be issued, but the row open

table is full and there is no bank/sub-bank match

between the current transaction and the row open table.

• The BSTOPRE interval expired for an open row.

Row open table misses

C2:1

Transactions that miss in the row open table

Row open table hits

C3:0

Transaction that hit in the row open table

Force page closings

C4:1

Forced page closings including those due to refreshes

Read-modify-write transactions due to

ECC

C5:0

If ECC is enabled and a transaction requires byte enables,

a read-modify-write sequence is issued on the DDR

SDRAM interface.

Forced page closings due to collision

with bank and sub-bank

Ref:12

Increments if a new transaction must be issued to an active

bank and sub-bank that has a different row open

Reads or writes from core

Ref:13

—

Reads or writes from TSEC 1

C3:1

—

Reads or writes from TSEC 2

C4:2

—

Table 19-10. Performance Monitor Events (continued)

Event Counted

Number

Description of Event Counted

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