MPC8540 datasheet(1097/1302 Pages) FREESCALE

1097 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

19-19

ECM dispatch from TSEC1

C3:19

—

ECM dispatch from TSEC2

C4:21

—

ECM dispatch from RapidIO

C5:17

—

ECM dispatch from PCI

C6:17

—

ECM dispatch from DMA

C7:14

—

ECM dispatch from other

C8:14

—

ECM dispatch to DDR

C4:22

—

ECM dispatch to L2/SRAM

C5:18

—

ECM dispatch to LBC

C6:18

—

ECM dispatch to RapidIO

C7:15

—

ECM dispatch to PCI

C8:15

—

ECM dispatch snoopable

C3:20

—

ECM dispatch write

C1:17

—

ECM dispatch write allocate

C2:21

—

ECM dispatch write allocate lock

C3:21

—

ECM dispatch read

C4:23

—

ECM dispatch read unlock

C5:19

—

ECM dispatch read clear atomic

C6:19

—

ECM dispatch read set atomic

C7:16

—

ECM dispatch read decrement atomic

C8:16

—

ECM dispatch read increment atomic

C7:17

—

ECM data bus grant DDR

C1:18

—

ECM data bus grant LBC

C2:22

—

ECM data bus grant PIC

C1:19

—

ECM data bus grant TSEC1

C3:23

—

ECM data bus grant TSEC2

C4:25

—

ECM data bus wait DDR

C5:20

—

ECM data bus wait LBC

C6:20

—

ECM data bus wait PIC

C5:21

—

ECM data bus wait TSEC1

C7:19

—

ECM data bus wait TSEC2

C8:18

—

ECM global data bus beat

Ref:16

—

Table 19-10. Performance Monitor Events (continued)

Event Counted

Number

Description of Event Counted

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