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MPC8540 Datasheet(PDF) 1101 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1101 Page - Freescale Semiconductor, Inc

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Functional Description
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
19-23
Dropped frames
Ref:38
Dropped frames that could have been accepted (data
overflow, status overflow and lack of BDs)
Dropped frames due to data overflow
C1:41
Frames dropped because of overflow in the FIFO and
256-byte buffer
Dropped frames due to status overflow
C2:50
Frames dropped because of inability to write status for one
frame and a new frame starts
TSEC1 FIFO Events
Receive FIFO data valid
C1:45
—
Transmit frames without threshold
C7:44
Transmit frames that do not hit Tx FIFO threshold
Receive FIFO above 1/4
Ref:47
—
Receive FIFO above 1/2
Ref:48
—
Receive FIFO above 3/4
Ref:49
—
DMA reads
C1:47
Descriptor and data reads
BD reads
C2:54
TxBD and RxBD reads
RxBD reads
C3:51
RxBD reads (transmit number can be calculated by
subtracting this number from total)
DMA writes
C4:52
Writes (descriptor and data)
BD writes
C5:46
TxBDs and RxBDs closed
RxBD writes
C6:49
RxBDs closed (transmit number can be calculated by
subtracting this number from total)
RxBD read latency
(duration threshold)
Ref:41
Times RxBD read latency exceeds threshold (threshold
event)
Start: request asserted
Stop: data acknowledge received
TxBD read latency
(duration threshold)
Ref:42
Times TxBD read latency exceeds threshold (threshold
event)
Start: request asserted
Stop: data acknowledge received
RxBD write latency
(duration threshold)
Ref:43
Times RxBD write latency exceeds threshold (threshold
event). Only for writes that require a response
Start: request asserted
Stop: end of transaction received
TxBD write latency
(duration threshold)
Ref:44
Times TxBD write response latency exceeds threshold
(threshold event). Only for writes that require a response
Start: request asserted
Stop: end of transaction received
Tx data read latency
(duration threshold)
Ref:45
Times data read response latency exceeds threshold
(threshold event)
Start: request asserted
Stop: data acknowledge received
Table 19-10. Performance Monitor Events (continued)
Event Counted
Number
Description of Event Counted



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