MPC8540 datasheet(1104/1302 Pages) FREESCALE

1104 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

19-26

Freescale Semiconductor

Performance Monitor

Atomic reservation time-outs for ECM

port

C6:54

—

Cycles a read is taking in GPCM

C1:53

—

Cycles a read is taking in UPM

C2:58

—

Cycles a read is taking in SDRAM

C3:57

—

Cycles a write is taking in GPCM

C4:56

—

Cycles a write is taking in UPM

C5:50

—

Cycles a write is taking in SDRAM

C6:55

—

SDRAM bank misses

C7:51

—

SDRAM page misses

C8:51

—

L2 Cache/SRAM Events

Core instruction accesses to L2 that hit

Ref:22

—

Core instruction accesses to L2 that

miss

C2:59

—

Core data accesses to L2 that hit

Ref:23

—

Core data accesses to L2 that miss

C4:57

—

Non-core burst write to L2 (cache

external write or SRAM)

C5:51

—

Non-core non-burst write to L2

C6:56

—

Noncore write misses cache external

write window and SRAM memory

range

C7:52

—

Non-core read hit in L2

Ref:24

—

Non-core read miss in L2

C1:54

—

L2 allocates, from any source

Ref:25

—

L2 retries due to full write queue

C2:60

—

L2 retries due to address collision

C3:58

—

L2 failed lock attempts due to full set

C4:58

—

L2 victimizations of valid lines

C5:52

—

L2 invalidations of lines

C6:57

—

L2 clearing of locks

C7:53

—

Debug Events

External event

C3:61

Number of cycles trig_in pin is asserted

Watchpoint monitor hits

C2:61

—

Table 19-10. Performance Monitor Events (continued)

Event Counted

Number

Description of Event Counted

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