MPC8540 datasheet(1108/1302 Pages) FREESCALE

1108 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

20-2

Freescale Semiconductor

Debug Features and Watchpoint Facility

Figure 20-1. Debug and Watchpoint Monitor Block Diagram

20.1.1 Overview

As shown in Figure 20-1, debug information is provided through the following interfaces:

PCI/PCI-X, LBC, and DDR SDRAM. Limited visibility, through a 256

× 64 trace buffer, is also

provided for the processor core interface and on an internal RapidIO outbound interface. This

visibility into internal device operation is useful for debugging application software through

inverse assembly and reconstruction of the fetch stream.

The combination of a source ID (MSRCID[0:4]) and a data-valid signal (MDVAL) indicates that

meaningful debug information is visible on either the local bus or DDR SDRAM interfaces. A

logic analyzer can be programmed to capture data based on the values of MSRCID[0:4] and

MDVAL.

e500 Coherency

PCI/PCI-X

Controller

RapidIO

e500 Processor

DDR

Controller

LBC

Controller

MECC[0:5]

MSRCID[0:4],

MDVAL

TRIG_IN

TRIG_OUT

PCI_AD[62:58]

Trace Buffer

(256 x 64)

Watchpoint

and trace

buffer control

Module

Core

SDRAM

Performance

Monitor

Signal name

LBC protocol signals

All other DDR signals

All other PCI signals

PORDBGMSR[MEM_SEL] =

POR value of MSRCID0

SRCID[0:4]

DVAL

SRCID[0:4]

DVAL

(Local Bus)

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