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MPC8540 Datasheet(PDF) 1111 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1111 Page - Freescale Semiconductor, Inc

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Introduction
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
20-5
20.1.3.3 PCI/PCI-X Interface Debug Modes
If PCI_GNT3 is low when sampled during POR, the PCI/PCI-X interface operates in debug mode.
In this mode, the source ID information appears on the high-order address bits (PCI_AD[62:58])
during the bus command phase. See Section 20.4.2, “PCI/PCI-X Interface Debug,” for more
information.
20.1.3.4 Watchpoint Monitor Modes
The watchpoint monitor supports the following operating modes:
•
Immediate trigger arming (one-level triggering)—The watchpoint monitor triggers as soon
as the first trigger event occurs.
•
Wait for trigger arming (two-level triggering)—The watchpoint monitor waits for a specific
event before enabling (arming) the trigger logic. The monitor does not respond to trigger
events until after the arming event occurs. This function is similar to two-level triggering
on a logic analyzer.
•
Assert TRIG_OUT on hit—The debug block can be programmed to assert the TRIG_OUT
signal when a programmed watchpoint monitor event occurs. This signal can be used to
trigger a logic analyzer.
20.1.3.5 Trace Buffer Modes
The trace buffer supports the following operating modes:
•
Immediate trigger arming (one-level triggering)—The trace buffer triggers as soon as the
first trigger event occurs.
•
Wait for trigger arming (two-level triggering)—The trace buffer waits for a specific event
before enabling (arming) the trigger logic. The trace buffer does not respond to trigger
events until after the arming event occurs. This function is similar to two-level triggering
on a logic analyzer.
•
Specific interface selection—The trace buffer can be programmed to trace one of several
internal interfaces.
•
Specific event selection—The trace buffer can be programmed to trace on the occurrence
of one or several concurrent events.
•
Specific trace selection—To facilitate trace data filtering, the trace buffer can be configured
to capture data under the following conditions:
— On every cycle in which a valid transaction is present on the selected interface
— Only when a watchpoint monitor event occurs
— Only when the programmed trace event is detected
•
Programmable trace stop—The trace buffer may be programmed to stop tracing when a
programmed stop-tracing event occurs or when the 256-entry buffer is full.



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