MPC8540 datasheet(1109/1302 Pages) FREESCALE

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Introduction

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-3

Othmer system debugging is supported by the programmable triggering of the watchpoint monitor

and trace buffer. Both can be triggered from one of the following three sources:

•

Each other

•

A performance monitor event

•

An external source (through TRIG_IN)

The watchpoint monitor can be configured to assert TRIG_OUT when a programmed event

occurs. The two context ID registers, described in Section 20.3.3, “Context ID Registers,” are

useful for software debug.

20.1.2 Features

The principle features of the debug modes and the watchpoint monitor are as follows:

•

PCI/PCI-X interface: transaction source ID driven onto PCI_AD[62:58]

•

LBC and DDR interface source ID and data-valid indicators

— LBC or DDR SDRAM source ID can be selected to be driven onto MSRCID[0:4]

— Source ID and data-valid indicators can be selected to be driven onto the error

correcting code (ECC) pins of the DDR interface

•

Watchpoint monitor that supports the following:

— Two-level triggering

— Programmable external trigger (TRIG_OUT)

— Interlocking with performance monitor to use its large number of counters

•

Trace buffer features that supports the following:

— Two-level triggering

— Programmable external trigger (TRIG_OUT)

— Interlocking with performance monitor to use its large number of counters

— 256-entry trace buffer, 64 bits each

— Programmable trace start and stop

— Functionality as a second watchpoint monitor

•

Context ID registers that can be programmed to trigger events

20.1.3 Modes of Operation

The PCI/PCI-X, LBC, and DDR SDRAM interfaces all have debug modes, which are controlled

by values on configuration inputs during the power-on reset (POR) sequence, as shown in

Table 20-3. The DDR controller can also drive debug information on either MSRCID[0:4] or

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