MPC8540 datasheet(1112/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

20-6

Freescale Semiconductor

Debug Features and Watchpoint Facility

20.2 External Signal Descriptions

This section provides information about all the external signals associated with the various

MPC8540 debug functions.

As shown in Table 20-1, the MPC8540 has several signals that are sampled during POR to

determine the configuration of the phase-locked loop clock mode and the ROM, Flash, and

dynamic memory. See Chapter 4, “Reset, Clocking, and Initialization.”

To facilitate system testing, the MPC8540 provides a JTAG test access port (TAP) that complies

with the IEEE 1149.1 boundary-scan specification. This section also describes JTAG TAP signals.

20.2.1 Overview

All the signals associated with device debug features are summarized in Table 20-2, listed with a

reference to the page number of the section with more information. The detailed descriptions are

contained in Table 20-2. Some signals (the MECC bus for example) are additionally described in

other chapters, but are described here also for completeness, with emphasis on their debugging

utility.

Table 20-2. Debug, Watchpoint and Test Signal Summary

Name

Description

Functional

Block

Function

Reset

Value

I/O Page #

MDVAL

Memory

data-valid

Debug

Selectable data-valid signal from either DDR SDRAM

controller or LBC

20-7

MECC[0:7]

DDR error

correcting

code

DDR

SDRAM

In debug mode, the 6 high-order bits carry debug

information (transaction source ID and data-valid

indication).

0x08

20-8

MSRCID[0:1]

Memory

source ID

Debug

Selectable transaction source ID from either DDR SDRAM

controller or local bus controller

Reset_cfg

20-8

MSRCID[2:4]

111

20-8

TRIG_IN

Trigger in

Debug

Trigger for various function in the watchpoint monitor and

trace buffer

20-8

TRIG_OUT

Trigger out

Debug

Can be used externally for triggering a logic analyzer.

Additionally, it can be used for observing system ready

indication. Functions are multiplexed onto this signal

depending on TOSR[SEL] (see Table 20-25).

20-8

PCI_AD[62:58] PCI address

Debug

In debug mode these pins carry the source ID of the

transaction.

0000_0

20-8

TCK

Test clock

Debug

Clock for JTAG testing. Internally pulled up

20-9

TDI

Test data

input

Debug

Serial input for instructions and data to the JTAG test

subsystem. Internally pulled up

20-9

TDO

Test data

output

Debug

Serial data output for the JTAG test subsystem. High

impedance except when scanning out data

Hi-Z

20-9

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