MPC8540 datasheet(1113/1302 Pages) FREESCALE

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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-7

20.2.2 Detailed Signal Descriptions

This section describes the details of the debug, watchpoint monitor, and JTAG test signals

20.2.2.1 Debug Signals—Details

Table 20-3 describes all signals associated with device debug modes.

TMS

Test mode

select

Debug

Carries commands to the TAP controller for boundary

scan operations. Internally pulled up

20-9

TRST

Test reset

Debug

Resets the TAP controller asynchronously

—

20-9

THERM[0:1]

Thermal

resistor

access

Test

These pins tie directly to an internal resistor whose value

varies linearly with temperature.

—I

20-9

TEST_SEL

Test select

Test

Factory test. Must be negated for normal operation

—

20-9

LSSD_

MODE

Test

Factory Test. Refer to the MPC8540 Integrated Processor

Hardware Specifications for proper treatment.

20-9

L1_TSTCLK

Test

Factory Test. Refer to the MPC8540 Integrated Processor

Hardware Specifications for proper treatment.

20-9

L2_TSTCLK

Test

Factory Test. Refer to the MPC8540 Integrated Processor

Hardware Specifications for proper treatment.

20-9

1 Although these signals are normally bidirectional, when sourcing debug information they are output only.

Table 20-3. Debug Signals—Detailed Signal Descriptions

Signal

I/O

Description

MDVAL

Memory data-valid. Indicates when valid data is available. May be used by a logic analyzer to capture the

data on the data bus.

State

Meaning

Asserted—Indicates that data is valid on the data bus during the current clock cycle. When the

DDR SDRAM interface is selected to source information on MDVAL, this signal is valid for

every cycle that data is driven or received on the DDR SDRAM interface. When the LBC

is selected, this signal is valid for every cycle that data is driven or received on the local

bus interface. The assertion of this signal may be used by a logic analyzer to capture data.

Timing Asserted/Negated—Referenced to the selected interface, (DDR or local bus). Asserts when

data is valid. Assertions are held for the duration of the transfer. Read data timing is similar

to MA. Write data timing is similar to the output MDQ.

Table 20-2. Debug, Watchpoint and Test Signal Summary (continued)

Name

Description

Functional

Block

Function

Reset

Value

I/O Page #

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