MPC8540 datasheet(1116/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

20-10

Freescale Semiconductor

Debug Features and Watchpoint Facility

20.3 Memory Map/Register Definition

Table 20-6 shows the memory-mapped debug and watchpoint registers of the MPC8540.

TRST

IJTAG test reset

State

Meaning

Asserted—Causes asynchronous initialization of the internal JTAG TAP controller. Must be

asserted during power-on reset in order to properly initialize the JTAG TAP and for normal

operation of the MPC8540. An unterminated input appears as a high signal level to the test

logic due to an internal pull-up resistor.

Negated— Normal operation

Timing See IEEE 1149.1 standard for more details

LSSD_MODE

Used for factory test. Refer to the MPC8540 Integrated Processor Hardware Specifications for proper

treatment.

L1_TSTCLK

Used for factory test. Refer to the MPC8540 Integrated Processor Hardware Specifications for proper

treatment.

L2_TSTCLK

Used for factory test. Refer to the MPC8540 Integrated Processor Hardware Specifications for proper

treatment.

THERM[0:1]

These signals provide access to an internal resistor that has a value that varies linearly with temperature.

The actual value for the resistor varies from device to device, but the linear relationship between

temperature and resistance is consistent. See the MPC8540 Integrated Processor Hardware Specifications

for more information on how to accurately measure the junction temperature of a device. Note that this

thermal resistor is intended for engineering development only.

TEST_SEL

Used for factory test. Must be negated for normal operation

Table 20-6. Debug and Watchpoint Monitor Memory Map

Local

Memory

Offset

Acces

Reset

Section/Page

Watchpoint Monitor Registers

0xE_2000

WMCR0—Watchpoint monitor control register 0

R/W

0x0000_0000

20.3.1.1/20-11

0xE_2004

WMCR1—Watchpoint monitor control register 1

R/W

0x0000_0000

20.3.1.1/20-11

0xE_200C

WMAR—Watchpoint monitor address register

R/W

0x0000_0000

20.3.1.2/20-13

0xE_2014

WMAMR—Watchpoint monitor address mask register

R/W

0x0000_0000

20.3.1.3/20-14

0xE_2018

WMTMR—Watchpoint monitor transaction mask register

R/W

0x0000_0000

20.3.1.4/20-14

0xE_201C

WMSR—Watchpoint monitor status register

R/W

0x0000_0000

20.3.1.5/20-16

Trace Buffer Registers

0xE_2040

TBCR0—Trace buffer control register 0

R/W

0x0000_0000

20.3.2.1/20-16

0xE_2044

TBCR1—Trace buffer control register 1

R/W

0x0000_0000

20.3.2.1/20-16

Table 20-5. JTAG Test and Other Signals—Detailed Signal Descriptions (continued)

Signal

I/O

Description

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