MPC8540 datasheet(1120/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

20-14

Freescale Semiconductor

Debug Features and Watchpoint Facility

Table 20-9 describes the WMAR fields.

20.3.1.3 Watchpoint Monitor Address Mask Register (WMAMR)

The watchpoint monitor address mask register (WMAMR) shown in Figure 20-5 contains the

mask that is applied to a transaction address before the address is compared with WMAR.

Table 20-10 describes the WMAMR fields.

20.3.1.4 Watchpoint Monitor Transaction Mask Register (WMTMR)

The watchpoint monitor transaction mask register (WMTMR), shown in Figure 20-6, specifies

which transaction types to monitor. WMTMR allows users to qualify watchpoint events

specifically with any combination of transaction types. As shown in Table 20-12, each bit

represents as many as four separate transaction types; one for each interface. Setting a bit enables

watchpoint monitoring for the corresponding transaction types.

Because the supported transaction types vary by interface, the type designated by a WMTMR field

also depends on the interface specified by WMCR1[IFSEL]. Table 20-12 lists transaction types

associated with each WMTMR bit by interface.

Table 20-9. WMAR Field Descriptions

Bits

Name

Description

0–31

WMA

Watchpoint monitor address.

WMAM

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_2014

Figure 20-5. Watchpoint Monitor Address Mask Register (WMAMR)

Table 20-10. WMAMR Field Descriptions

Bits

Name

Description

0–31

WMAM Watchpoint monitor address mask. A value of zero masks the address comparison for the

corresponding address bit.

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