MPC8540 datasheet(1122/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

20-16

Freescale Semiconductor

Debug Features and Watchpoint Facility

20.3.1.5 Watchpoint Monitor Status Register (WMSR)

The watchpoint monitor status register (WMSR) shown in Figure 20-7 indicates the state of the

watchpoint monitor.

Table 20-13 describes the WMSR fields.

20.3.2 Trace Buffer Register Descriptions

The following sections describes the trace buffer registers.

20.3.2.1 Trace Buffer Control Registers (TBCR0, TBCR1)

The trace buffer control registers (TBCR0, TBCR1), shown in Figure 20-8 and Figure 20-9,

specify trace buffer events.

—

MAINTENANCE

read

—

DOORBELL

—

MESSAGE

ACT TRIG

0 0

0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_201C

Figure 20-7. Watchpoint Monitor Status Register (WMSR)

Table 20-13. WMSR Field Descriptions

Bits

Name

Description

0ACT

Active

0 The start triggering event has not occurred; watchpoint monitor is not armed.

1 The start triggering event has occurred; watchpoint monitor is armed.

TRIG

Triggered

0 The programmed event in WMCR0 has not yet been triggered.

1 The programmed event in WMCR0 has been triggered at least once.

2–31

—

Reserved

Table 20-12. Transaction Types by Interface (continued)

Bit

e500 Coherency Module Dispatch

DDR Controller

PCI

Outbound

Request

RapidIO

Outbound

Request

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