MPC8540 datasheet(1126/1302 Pages) FREESCALE

1126 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

20-20

Freescale Semiconductor

Debug Features and Watchpoint Facility

Table 20-17 describes the TBAMR field.

20.3.2.4 Trace Buffer Transaction Mask Register (TBTMR)

The trace buffer transaction mask register (TBTMR) shown in Figure 20-12 specifies which

transaction types to monitor. Each bit in the TBTMR represents a transaction type on the selected

interface. The transaction associated with any particular bit depends on the interface being

monitored as specified by TBCR1[IFSEL]. Note that the transactions used for defining trace

buffer events are the same as those defined for watchpoint monitor events. Thus, Table 20-12

defines the transaction types associated with each interface. Setting a bit enables a hit when this

transaction is matched (provided all other match criteria are met and TBCR0[TMD] is clear).

Different interfaces support different transaction types, and the same bit may represent different

transaction types depending on the interface.

TBAM

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_2054

Figure 20-11. Trace Buffer Address Mask Register (TBAMR)

Table 20-17. TBAMR Field Descriptions

Bits

Name

Description

0–31

TBAM Trace buffer address mask.A value of zero masks the address comparison for the corresponding

address bit.

TBTM

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_2058

Figure 20-12. Trace Buffer Transaction Mask Register (TBTMR)

MPC8540 Datasheet(PDF) 1126 Page - Freescale Semiconductor, Inc