MPC8540 datasheet(1125/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-19

Table 20-15 describes the TBCR1 fields.

20.3.2.2 Trace Buffer Address Register (TBAR)

The trace buffer address register (TBAR) shown in Figure 20-10 contains the address to match

against (if TBCR0[AMD] is zero). The transaction address is qualified with the bits described in

Section 20.3.2.3, “Trace Buffer Address Mask Register (TBAMR),” before being compared with

TBAR. Note that the contents of TBAR are not qualified with TBAMR.

Table 20-16 describes the TBAR field.

20.3.2.3 Trace Buffer Address Mask Register (TBAMR)

The trace buffer address mask register (TBAMR) shown in Figure 20-11 contains the mask that is

applied to a transaction address before the address is compared with TBAR.

Table 20-15. TBCR1 Field Descriptions

Bits

Name

Description

0–4

—

Reserved

5–7

IFSEL Interface selection. Specifies the interface that sources information for both comparison/buffer control and

buffer data capture

000 Selects e500 coherency module (ECM) dispatch interface

001 Selects internal DDR SDRAM interface

010 Selects internal PCI outbound interface

011 Selects internal RapidIO interface

1xx Reserved

8–10

—

Reserved

11–15

SID

Source ID. Specifies the source ID associated with TBCR0[SIDEN]. The source ID is defined in Table 20-26.

16–26

—

Reserved

27–31

TID

Target ID. Specifies the target ID associated with TBCR0[TIDEN]. The target ID is defined in Table 20-26.

TBA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_204C

Figure 20-10. Trace Buffer Address Register (TBAR)

Table 20-16. TBAR Field Descriptions

Bits

Name

Description

0–31

TBA

Trace buffer address

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