MPC8540 datasheet(1121/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-15

Table 20-11 describes the WMTMR fields.

The following table defines the transactions associated with each transaction mask bit for the

different interfaces supported by the watchpoint monitor.

WMTM

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_2018

Figure 20-6. Watchpoint Monitor Transaction Mask Register (WMTMR)

Table 20-11. WMTMR Field Descriptions

Bits

Name

Description

0–31

WMTM

Watchpoint monitor transaction mask. Each bit corresponds to a transaction type as defined in

Table 20-12. The transaction associated with any particular bit may be different depending on the

interface being monitored. A value of 1 for a given mask bit enables the matching of the transaction

associated with that bit. These bits are meaningful only when WMCR0[TMD]=0.

Table 20-12. Transaction Types by Interface

Bit

e500 Coherency Module Dispatch

DDR Controller

PCI

Outbound

Request

RapidIO

Outbound

Request

Write with local processor snoop

Write

Memory write

NWRITE

Write with no local processor snoop

—

I/O write

NWRITE_R

Write with allocate (L2 stashing)

Write with allocate

—

SWRITE

Write with allocate and lock (L2 stashing with

locking)

Write with allocate and lock

—

FLUSH with data

4–7

Reserved

Read with local processor snoop

Read

Memory Read

NREAD

Read with no local processor snoop

—

I/O Read

IO_READ_HOME

Read with unlock

—

11–15

Reserved

Atomic clear

ATOMIC clear

—

ATOMIC clear

Atomic set

ATOMIC set

—

ATOMIC set

Atomic decrement

ATOMIC decrement

—

ATOMIC decrement

Atomic increment

ATOMIC increment

—

ATOMIC increment

20–27

Reserved

—

MAINTENANCE

write

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