MPC8540 datasheet(1124/1302 Pages) FREESCALE

1124 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

20-18

Freescale Semiconductor

Debug Features and Watchpoint Facility

HALT

Halt causes the trace buffer to stop tracing immediately.

8–13

—

Reserved

14–15

MODE

Trace mode. Specifies one of two trace modes

00 Trace every valid transaction

01 Reserved

10 Trace only cycles in which a trace event is detected. Note that if EN and other TBCR0 fields are not

properly programmed to specify a traceable event, tracing occurs for every valid address.

11 Reserved

16–20

—

Reserved

21–23

STRT

Start condition. Specifies the event that arms the trace buffer to start looking for the programmed event.

000 No event. Armed immediately

001 Watchpoint monitor event is detected

010 Trace buffer event is detected

011 Performance monitor signals overflow

100 TRIG_IN transitions from 0 to 1.

101 TRIG_IN transitions from 1 to 0.

110 Current context ID equals programmed context ID

111 Current context ID does not equal programed context ID

24–28

—

Reserved

29–31

STOP

Trace stop mode. Specifies the event that stops the updating of the trace buffer after it has been started.

Trace buffer only stops after it has been triggered at least once.

000 Buffer is full

001 Watchpoint monitor event is detected

010 Trace buffer event is detected

011 Performance monitor signals overflow

100 TRIG_IN transitions from 0 to 1.

101 TRIG_IN transitions from 1 to 0.

110 Current context ID equals programmed context ID

111 Current context ID does not equal programed context ID

10 11

15 16

26 27

R 0

IFSEL

SID

0 0 0 0 0 0 0 0 0 0 0

TID

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_2044

Figure 20-9. Trace Buffer Control Register 1 (TBCR1)

Table 20-14. TBCR0 Field Descriptions (continued)

Bits

Name

Description

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