MPC8540 datasheet(1119/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-13

Figure 20-3 shows the WMCR1.

Table 20-8 describes the WMCR1 fields.

20.3.1.2 Watchpoint Monitor Address Register (WMAR)

The watchpoint monitor address register (WMAR) shown in Figure 20-4 contains the address to

match against if WMCR[AMD] is clear. Note that the transaction address is qualified with the bits

described in Section 20.3.1.3, “Watchpoint Monitor Address Mask Register (WMAMR),” before

being compared with WMAR. Note also that the contents of WMAR are not qualified with

WMAMR.

012

10 11

15 16

26 27

R 0

IFSEL

0 0 0

SID

TID

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_2004

Figure 20-3. Watchpoint Monitor Control Register 1 (WMCR1)

Table 20-8. WMCR1 Field Descriptions

Bits

Name

Description

0–4

—

Reserved

5–7

IFSEL

Interface selection. Selects the address, transaction type (as defined in WMTMR), and other

attributes to be used for comparison

000 Select e500 coherency module (ECM) dispatch interface

001 Select internal DDR SDRAM interface

010 Select internal PCI outbound interface

011 Select internal RapidIO interface

1xx Reserved

8–10

—

Reserved

11–15

SID

Source ID. Specifies the source ID associated with WMCR0[SIDEN]. For a definition of the source

ID, see Table 20-26.

16–26

—

Reserved

27–31

TID

Target ID. Specifies the target ID associated with WMCR0[TIDEN]. For a definition of the target ID,

see Table 20-26.

WMA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_200C

Figure 20-4. Watchpoint Monitor Address Register (WMAR)

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