MPC8540 datasheet(1117/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-11

20.3.1 Watchpoint Monitor Register Descriptions

The following sections describe the control registers for the watchpoint monitor facility.

20.3.1.1 Watchpoint Monitor Control Registers 0–1 (WMCR0, WMCR1)

The watchpoint monitor control registers (WMCR0, WMCR1) shown in Figure 20-2 and

Figure 20-3 control the specification of watchpoint monitor events.

0xE_204C

TBAR—Trace buffer address register

R/W

0x0000_0000

20.3.2.2/20-19

0xE_2054

TBAMR—Trace buffer address mask register

R/W

0x0000_0000

20.3.2.3/20-19

0xE_2058

TBTMR—Trace buffer transaction mask register

R/W

0x0000_0000

20.3.2.4/20-20

0xE_205C

TBSR—Trace buffer status register

R/W

0x0000_0000

20.3.2.5/20-21

0xE_2060

TBACR—Trace buffer access control register

R/W

0x0000_0000

20.3.2.6/20-22

0xE_2064

TBADHR—Trace buffer access data high register

R/W

0x0000_0000

20.3.2.7/20-22

0xE_2068

TBADR—Trace buffer access data register

R/W

0x0000_0000

20.3.2.8/20-23

Context ID Registers

0xE_20A0

PCIDR—Programmed context ID register

R/W

0x0000_0000

20.3.3.1/20-24

0xE_20A4

CCIDR—Current context ID register

R/W

0x0000_0000

20.3.3.2/20-24

Other Registers

0xE_20B0

TOSR—Trigger output source register

R/W

0x0000_0000

20.3.4.1/20-25

20 21

23 24

EN AMD TMD ECEN NECEN SIDEN TIDEN

0 0 0 0 0 0 0 0 0 0 0 0 0 0

STRT

0 0 0 0 0 0 0 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_2000

Figure 20-2. Watchpoint Monitor Control Register 0 (WMCR0)

Table 20-6. Debug and Watchpoint Monitor Memory Map (continued)

Local

Memory

Offset

Acces

Reset

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