MPC8540 datasheet(1114/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

20-8

Freescale Semiconductor

Debug Features and Watchpoint Facility

20.2.2.2 Watchpoint Monitor Trigger Signals—Details

Table 20-4 shows detailed descriptions of the watchpoint monitor and trace buffer signals.

MECC[0:7]

Memory ECC. DDR error checking and correcting. The normally bidirectional operation of the memory ECC

(MECC) bus is described in Section 9.5.11, “Error Checking and Correcting (ECC).” This bus is used for

debug functions when MSRCID1 is sampled low during POR.

In debug mode, the high-order 5 bits (MECC[0:4]) may be used to provide the transaction source ID and

MECC5 can be used as the data-valid indicator.

In debug mode, MECC[0:5] is constantly driven with debug information and must be disconnected from the

DDR memory’s ECC pins.

State

Meaning

Asserted/Negated—In debug mode, MECC[0:5] is always driven. The source ID values appear

during RAS and CAS cycles. A value of 0x1F (all ones) is driven during cycles other than

RAS and CAS. The data-valid indicator appears when data is being received or driven on

the pins.

Timing Driven every cycle in debug mode

MSRCID[0:4]

Memory source ID. Attribute signals associated with the memory interface that indicate the source ID for a

transaction on an SDRAM interface. The SDRAM interface, DDR or local bus, to which the debug

information applies is specified during POR with MSRCID0 as shown in Table 20-1. Two of these signals

serve as reset configuration input signals.

State

Meaning

Asserted/Negated—In debug mode, always driven with the value of the source ID. The source

ID has a value of 0x1F for cycles other than RAS and CAS. The encodings shown in

Table 20-26 provide detailed information about a memory transaction.

Timing Driven every cycle in debug mode. Similar timing to MA

PCI_AD[62:58]

PCI Address. Provides transaction source ID for the current PCI bus transaction

State

Meaning

Asserted/Negation—In debug mode, always driven with the value of the transaction source ID

Timing Driven every cycle in debug mode

Table 20-4. Watchpoint and Trigger Signals—Detailed Signal Descriptions

Signal

I/O

Description

TRIG_IN

Trigger in. Can be used to trigger the watchpoint and trace buffers. Note this is an active-high (rising-edge

triggered) signal.

State

Meaning

Asserted—Indicates that a programmed/armed external event has been detected. Assertion

may be used internally to trigger trace buffers and watchpoint mechanisms.

Timing Assertion/Negation—The MPC8540 interprets TRIG_IN as asserted on detection of the rising

edge. It may occur at any time. Must remain asserted for at least 3 system clocks to be

recognized internally

Table 20-3. Debug Signals—Detailed Signal Descriptions (continued)

Signal

I/O

Description

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