MPC8540 datasheet(1115/1302 Pages) FREESCALE

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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-9

20.2.2.3 Test Signals—Details

Table 20-5 shows detailed descriptions of the JTAG test signals.

TRIG_OUT

Trigger out. Function determined by TOSR[SEL]. When TOSR[SEL] is non-zero, it can be used for

triggering external devices, like a logic analyzer, with either the watchpoint monitor, the trace buffer, or the

performance monitor as trigger sources. When TOSR[SEL] is cleared, TRIG_OUT is multiplexed with

READY, which indicates the operational readiness of the device (running or in low-power or debug modes).

See Chapter 4, “Reset, Clocking, and Initialization,” and Chapter 18, “Global Utilities,” for more details

about reset, low power, and debug states.

State

Meaning

Asserted—When TOSR[SEL] is all zeros, serves as the READY signal, indicating that the

device is not in a low-power or debug mode and that it has emerged from reset. SEL

≠ 0

indicates that a programmed trigger event has occurred.

Negation—No final watchpoint match condition

Timing Assertion may occur at any time. Remains asserted for at least 3 system clocks

Table 20-5. JTAG Test and Other Signals—Detailed Signal Descriptions

Signal

I/O

Description

TCK

JTAG test clock

State

Meaning

Asserted/Negated—Should be driven by a free-running clock signal with a 30–70% duty cycle.

Input signals to the TAP are clocked in on the rising edge. Changes to the TAP output

signals occur on the falling edge. The test logic allows TCK to be stopped. An unterminated

input appears as a high signal level to the test logic due to an internal pull-up resistor.

Timing See IEEE 1149.1 standard for more details

TDI

JTAG test data input

State

Meaning

Asserted/Negated—The value present on the rising edge of TCK is clocked into the selected

JTAG test instruction or data register. An unterminated input appears as a high signal level

to the test logic due to an internal pull-up resistor.

Timing

See IEEE 1149.1 standard for more details

TDO

JTAG test data output

State

Meaning

Asserted/Negated—The contents of the selected internal instruction or data register are shifted

out on this signal on the falling edge of TCK. Remains in a high-impedance state except

when scanning data.

Timing See IEEE 1149.1 standard for more details

TMS

JTAG test mode select

State

Meaning

Asserted/Negated—Decoded by the internal JTAG TAP controller to distinguish the primary

operation of the test support circuitry. An unterminated input appears as a high signal level

to the test logic due to an internal pull-up resistor.

Timing See IEEE 1149.1 standard for more details

Table 20-4. Watchpoint and Trigger Signals—Detailed Signal Descriptions (continued)

Signal

I/O

Description

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