MPC8540 datasheet(1129/1302 Pages) FREESCALE

1129 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-23

Table 20-21 describes TBADHR.

20.3.2.8 Trace Buffer Access Data Register (TBADR)

The trace buffer access data register (TBADR), shown in Figure 20-16, contains the low-order 32

bits of the data read from the trace buffer during a software-initiated read command

(TBACR[RD]) or the write data to be written into the trace buffer during a software-initiated write

command (TBACR[WR]). TBACR must be configured to perform a read before this register

contains valid data. This register must be initialized by software before configuring the TBACR

to perform a write command.

Table 20-22 describes the TBADR field.

TBADH

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_2064

Figure 20-15. Trace Buffer Read High Register (TBADHR)

Table 20-21. TBADHR Field Descriptions

Bits

Name

Description

0–31

TBADH Trace buffer access data high. The higher 32 bits of the data read from or to be written into the trace

buffer, depending on whether the array is accessed with a read or a write.

TBAD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_2068

Figure 20-16. Trace Buffer Access Data Register (TBADR)

Table 20-22. TBADR Field Descriptions

Bits

Name

Description

0–31

TBAD Trace buffer access data. Corresponds to the lower 32 bits of the data read from the trace buffer or to be

written into the trace buffer, depending on whether software is accessing the array with a read or a write.

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