MPC8540 datasheet(1133/1302 Pages) FREESCALE

1133 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-27

20.4.2 PCI/PCI-X Interface Debug

If PCI_GNT3 is low when sampled during POR, the PCI/PCI-X interface operates in debug mode.

In debug mode the source ID appears on the high-order address bits (PCI_AD[62:58]) during the

bus command phase of a PCI/PCI-X transaction. The bus command phase occurs either during the

first cycle that PCI_FRAME is asserted, or, in the case of addresses greater than 32 bits, after a

dual-address cycle phase. In either case, the debug information appears on the highest order

address bits while PCI_FRAME is asserted and both PCI_IRDY and PCI_TRDY are negated.

When accessing the low 4 Gbytes of PCI address space for which no dual-address cycle is needed,

the debug information appears during the first (and only) address phase on PCI_AD[62:58].

Whenever a dual-address cycle must be run, (addresses above 4 Gbytes) the debug information

appears on PCI_AD[62:58] during the second address cycle. In either case a logic analyzer should

be configured to sample information on the first cycle of the assertion of PCI_FRAME and the

cycle following a dual-address cycle command.

NOTE

Because they share the same pins, an entire 64-bit address and the

debug information cannot be captured in a single cycle.

Reserved

Local bus controller

Reserved

DMA

Reserved

System access port (SAP)

Configuration space

TSEC1

Reserved

TSEC2

Boot sequencer

FEC

Reserved

RapidIO

RapidIO message unit

Reserved

RapidIO doorbell unit

Reserved

RapidIO port-write unit

Local space (DDR)

Non valid port indicator (reserved for debug info)

Table 20-26. Source and Target ID Values (continued)

Value

(Hex)

Source (or Target) Port

Value

(Hex)

Source (or Target) Port

MPC8540 Datasheet(PDF) 1133 Page - Freescale Semiconductor, Inc

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