MPC8540 datasheet(1137/1302 Pages) FREESCALE

1137 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-31

Figure 20-21 shows the trace buffer entry format for the DDR SDRAM interface,

TBCR1[IFSEL] = 001.

Table 20-28 describes the fields of DDR SDRAM trace buffer entries when

TBCR1[IFSEL] = 001.

14–18

CMDBC

Byte count. Range: 32 to 1 where a value of 0 indicates 32 bytes.

00000 32 bytes

00001 1 byte

00010 2 bytes

·· ·

11110 30 bytes

11111 31 bytes

19–31

—

Reserved

32–63

CMDADDR

Address bits 0–31

13 14

18 19

31 32

DDRTT

DDRSID

—

DDRBC

—

DDRADDR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Figure 20-21. DDR Trace Buffer Entry

Table 20-28. DDR Trace Buffer Entry Field Descriptions

(TBCR1[IFSEL] = 001)

Bits

Name

Function

0–4

DDRTT

Transaction type. Specifies the transaction type as shown in Table 20-12. For example, a value

of all zeros maps to write.

5–9

DDRSID

Source ID. Specifies the source of the transaction as shown in Table 20-26. For example, a

value of 01100 indicates that RapidIO is the transaction source, and so on.

10–13

—

Reserved

14–18

DDRBC

Byte count

19–31

—

Reserved

32–63

DDRADDR

Address bits 0–31

Table 20-27. CMD Trace Buffer Entry Field Descriptions

(TBCR1[IFSEL] = 000) (continued)

Bits

Name

Function

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