MPC8540 datasheet(1134/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

20-28

Freescale Semiconductor

Debug Features and Watchpoint Facility

20.4.3 DDR SDRAM Interface Debug

The DDR interface has two debug modes distinguished by which pins drive the debug

information. In one mode, debug information (source ID, data valid) is multiplexed onto the ECC

pins; the other mode uses the debug pins.

20.4.3.1 Debug Information on Debug Pins

If MSRCID0 is high when sampled during POR, the debug information from the DDR SDRAM

interface is driven on MSRCID[0:4] and MDVAL. This POR value is captured in

PORDBGMSR[MEM_SEL] as described in Section 18.4.1.5, “POR Debug Mode Status Register

(PORDBGMSR).” In this mode, the source ID appears on MSRCID[0:4] during a RAS or CAS

cycle. During any other cycle, the value of MSRCID[0:4] is all ones, which indicates idle cycles

on the address/command interface. Similarly, MDVAL is asserted during valid data cycles on the

DDR interface.

20.4.3.2 Debug Information on ECC Pins

If MSRCID1 is low when sampled during POR, debug information from the DDR SDRAM

interface is selected to appear on MECC[0:5] as shown in Figure 20-1. In this mode, the ID value

of the source port, (the source ID), appears on MECC[0:4] during a RAS or CAS cycle. During

any other cycle the value of MECC[0:4] is all ones. A data-valid signal (DVAL) is driven on

MECC5 during valid DDR SDRAM data cycles.

NOTE

In this mode, MECC[0:5] must be disconnected from all SDRAM

devices to prevent contention on those lines.

20.4.4 Local Bus Interface Debug

If MSRCID0 is low when sampled during POR, the LBC is selected as the source for the debug

information appearing on MSRCID[0:4] and MDVAL. For more information on this mode, see

Section 13.1.3.2, “Source ID Debug Mode.”

20.4.5 Watchpoint Monitor

The watchpoint monitor (WM) can be programmed to arm and trigger on many different events

including any of the following:

•

External event (through TRIG_IN)

•

A trace buffer event

•

A performance monitor overflow event

•

A comparison of the current and programmed context ID registers

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