MPC8540 datasheet(1138/1302 Pages) FREESCALE

1138 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

20-32

Freescale Semiconductor

Debug Features and Watchpoint Facility

Figure 20-22 shows the PCI trace buffer entry format when TBCR1[IFSEL] = 010.

Table 20-29 describes the fields of PCI trace buffer entries when TBCR1[IFSEL] = 010.

Figure 20-23 shows the format for RapidIO interface trace buffer entries when

TBCR1[IFSEL] = 011.

Table 20-30 describes the fields of the RapidIO interface trace buffer entries.

31 32

PCITT

PCISID

PCIBC

—

PCIADDR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Figure 20-22. PCI Trace Buffer Entry

Table 20-29. PCI Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 010)

Bits

Name

Function

0–4

PCITT

Transaction type. Specifies the transaction type as shown in Table 20-12. For example, a value

of all zeros maps to write.

5–9

PCISID

Source ID. Identifies the source of the transaction as shown in Table 20-26. For example, a

value of 01100 identifies RapidIO as the transaction source.

10–11

PCIBC

Byte count. The size of the transaction.

00 32 bytes

01 8 bytes

10 16 bytes

11 24 bytes

12–31

—

Reserved

32–63 PCIADDR Address bits 0–31

13 14

18 19

32 33

RIOTT

RIOSID

—

RIODWC

RIOADDR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Figure 20-23. RapidIO Trace Buffer Entry

Table 20-30. RapidIO Trace Buffer Entry Field Descriptions

(TBCR1[IFSEL] = 011)

Bits

Name

Function

0–4

RIOTT

Transaction type. Specifies the transaction type as shown in Table 20-12. For example, a value

of all zeros indicates an NWRITE transaction.

5–9

RIOSID

Source ID. Identifies the source of the transaction as shown in Table 20-26. For example, a

value of 01100 identifies RapidIO as the transaction source.

—

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