MPC8540 datasheet(1135/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-29

A watchpoint event can be used in the following ways:

•

Trigger a logic analyzer (using TRIG_OUT)

•

Arm or trigger the trace buffer

•

Trigger a performance monitor event

The large counters available in the performance monitor block and the interlock between it and the

watchpoint monitor support sophisticated debug scenarios.

A WM trigger event may be composed of several events programmed in the watchpoint monitor

control registers (WMCR0–WMCR1). Because the watchpoint monitor is disabled by default

during POR, these registers must be initialized to make use of this debug feature. Note that the

WM address mask register (WMAMR) and the type mask register (WMTMR) are cleared during

POR. This means that the watchpoint monitor’s default behavior following a power-on reset is to

trigger on any address and no transaction type. The reset value of WMCR0[TMD] is 0 which

means transaction matching is enabled but since no transaction is selected (WMTMR=0), a match

will never occur. Either the transaction matching must be disabled by setting WMCR0[TMD] to a

value of 1, or valid transactions must be selected by setting one or more of the WMTMR bits to a

value of 1.

20.4.5.1 Watchpoint Monitor Performance Monitor Events

The WM can produce a performance monitor (PM) event with every trigger. This is accomplished

by configuring the performance monitor to count WM events. For more information on this

configuration see the events named “Number of watchpoint monitor hits,” and “Number of trace

buffer hits,” in Table 19-10.

Multi-level triggers can be created using the watchpoint monitor, the performance monitor, and

the trace buffer combined. For example, the WM can be programmed to trigger on events that also

increment a PM counter (the performance monitor must also be programmed to respond to this

event), the output of which (perfmon_overflow) could trigger the start of tracing in the trace buffer.

20.4.6 Trace Buffer

The trace buffer is a 256

× 64 array that can capture information about the internal processing of

transactions to selected interfaces. The trace buffer controls are a superset of those for the

watchpoint monitor. Close inspection of the trace buffer control registers (TBCRn) and the WM

control registers (WMCRn) shows that trace buffer controls not needed for the WM are marked

reserved in WMCRn. This permits using the trace buffer as a second watchpoint monitor by

simply ignoring the trace options.

The trace buffer provides great flexibility about when to start tracing, when to stop tracing, and

what to trace. The trace mode field, TBCR0[MODE], indicates when to trace: on every valid cycle,

on a watchpoint monitor event, or when all the programmed events in the TBCR are met. This

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