MPC8540 datasheet(1132/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

20-26

Freescale Semiconductor

Debug Features and Watchpoint Facility

Table 20-25 describes the TOSR fields.

20.4 Functional Description

The debug features on the MPC8540 use the LBC interfaces, DDR SDRAM interface, and the PCI

interface.

20.4.1 Source and Target ID

Debug information that is common to all the interfaces is the source ID (SID). The transaction

source ID provides enough information to determine which block or port originated a transaction

including the distinction between instruction and data fetches from the processor core. Table 20-26

shows the values and interpretation for the 5-bit SID field. Note that the table also includes ports

that are only slaves, such as local memory. These ports are always targets. As such, the value

shown represents a target ID (TID) and not a source ID. For ports that can function in both

capacities, the value indicates source ID when mastering transactions, and target ID when

responding as slave. The TID field is only meaningful when one of the following participates in

the transaction:

•

The e500 coherency module (ECM) dispatch bus

•

The watchpoint monitor (WMCR1[IFSEL] = 000)

•

The trace buffer (TBCR1[IFSEL] = 000)

Table 20-25. TOSR Field Descriptions

Bits

Name

Description

0–4

—

Reserved

5–7

SEL

Select. Selects the source for TRIG_OUT

000 READY signal. Multiplexed with TRIG_OUT. Basic device state indicator. READY asserts

whenever the device is not in reset or not asleep. See Chapter 4, “Reset, Clocking, and

Initialization,” for more details about the reset sequence, and Chapter 18, “Global Utilities,” for

more information about power management states.

001 Selects the watchpoint monitor hit indication

010 Selects the trace buffer hit indication

011 Selects the performance monitor overflow indication

8–31

—

Reserved

Table 20-26. Source and Target ID Values

Value

(Hex)

Source (or Target) Port

Value

(Hex)

Source (or Target) Port

PCI/PCI-X

Local processor (instruction fetch)

Reserved

Local processor (data fetch)

Reserved

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