MPC8540 datasheet(1107/1302 Pages) FREESCALE

1107 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

20-1

Chapter 20

Debug Features and Watchpoint Facility

This chapter describes all customer-visible debug modes of the MPC8540 integrated device. The

debug features on the MPC8540 pertain to these three interfaces: the local bus controller (LBC),

the DDR SDRAM, and the PCI/PCI-X interface. In addition to the external interfaces, the

MPC8540 provides triggering capabilities based on user-programmable events. The watchpoint

and trace buffer also provide some visibility to internal buses. This chapter also describes context

ID registers, useful for software debug, and describes the JTAG access port signals that comply

with the IEEE 1149.1 boundary-scan specification.

20.1 Introduction

As shown in the block diagram of Figure 20-1, the MPC8540 device provides the following debug

features (listed with references to sections of this chapter that describe them):

•

PCI/PCI-X interface debug (Section 20.4.2, “PCI/PCI-X Interface Debug”)

•

DDR SDRAM interface debug (Section 20.4.3, “DDR SDRAM Interface Debug”)

•

Local bus controller (LBC) debug (Section 20.4.4, “Local Bus Interface Debug”)

•

Watchpoint monitor and trace buffer debug (Section 20.4.5, “Watchpoint Monitor,” and

Section 20.4.6, “Trace Buffer”)

MPC8540 Datasheet(PDF) 1107 Page - Freescale Semiconductor, Inc