MPC8540 datasheet(1105/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

19-27

19.4.8 Performance Monitor Examples

Table 19-12 contains sample register settings for the four supported modes.

•

Simple event performance monitoring example

•

Triggering event performance monitoring example

•

Threshold event performance monitoring example

•

Burstiness event performance monitoring example

The settings in Table 19-11 are identical for all four examples.

For simple event counting, a non-threshold event is selected in PMLCAn[EVENT] and all other

features are disabled by clearing all register fields except for CE.

Trace buffer hits

C1:58

—

DUART Events

UART0 baud rate

C1:63

—

UART1 baud rate

C5:63

—

Chaining Events

PMC0 carry-out

Ref:1

PMC0[0] 1-to-0 transitions

PMC1 carry-out

Ref:2

PMC1[0] 1-to-0 transitions. Reserved for PMC1.

PMC2 carry-out

Ref:3

PMC2[0] 1-to-0 transitions. Reserved for PMC2.

PMC3 carry-out

Ref:4

PMC3[0] 1-to-0 transitions. Reserved for PMC3.

PMC4 carry-out

Ref:5

PMC4[0] 1-to-0 transitions. Reserved for PMC4.

PMC5 carry-out

Ref:6

PMC5[0] 1-to-0 transitions. Reserved for PMC5.

PMC6 carry-out

Ref:7

PMC6[0] 1-to-0 transitions. Reserved for PMC6.

PMC7 carry-out

Ref:8

PMC7[0] 1-to-0 transitions. Reserved for PMC7.

PMC8 carry-out

Ref:9

PMC8[0] 1-to-0 transitions. Reserved for PMC8.

Table 19-11. PMGC0 and PMLCAn Settings

Field

Setting

Reason

PMGC0[FAC]

Counters must not be frozen.

PMGC0[PMIE]

Performance monitor interrupts are enabled.

PMGC0[FCECE]

Counters should be frozen when an interrupt is signalled.

PMLCAn[FC]

Counters cannot be frozen for counting.

PMLCAn[CE]

Overflow condition enable is required to allow interrupt signalling.

Table 19-10. Performance Monitor Events (continued)

Event Counted

Number

Description of Event Counted

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