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MPC8540 Datasheet(PDF) 1106 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1106 Page - Freescale Semiconductor, Inc |
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1106 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 19-28 Freescale Semiconductor Performance Monitor For the triggering example any event can be selected in PMLCAn[EVENT]. All other features are disabled by clearing these register fields except for CE to allow interrupt signalling. If PMLCBn[TRIGONSEL] is 3 and PMLCBn[TRIGOFFSEL] is 5, the counter begins and ends counting based on the conditions in counters three and five. Furthermore, if PMLCBn[TRIGONCNTL] is 1, the counter begins counting when PMC3 changes value. According to the setting in PMLCBn[TRIGOFFCNTL], the counter ends counting when PMC5 overflows. Also, although the register settings for PMC5 is not shown, PMLCAn[CE] for this counter must be cleared so that interrupt signalling is not enabled and the counter does not freeze when it overflows. For threshold counting, a threshold event must be specified in PMLCAn[EVENT]. For this example, the duration threshold value is scaled by two because PMLCBn[TBMULT] is one. All other features are disabled by clearing the appropriate fields. Any non-threshold event can use the burstiness feature. For burstiness counting, values for PMLCAn[BSIZE,BGRAN,BDIST] and PMLCBn[TBMULT] must be specified. Table 19-12. Register Settings for Counting Examples MPC8540 Register Register Field Simple Event Triggering Threshold Burstiness PMGC0 FAC 0 0 0 0 PMIE 111 1 FCECE 111 1 PMLCAn FC 000 0 CE 111 1 EVENT 89 68 39 2 BSIZE 0 0 0 5 BGRAN 000 1 BDIST 000 8 PMLCBn TRIGONSEL 0 3 0 0 TRIGOFFSEL 0 5 0 0 TRIGONCNTL 0 1 0 0 TRIGOFFCNTL 0 2 0 0 TBMULT 000 0 THRESHOLD 0 0 3 0 |
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