MPC8540 datasheet(1103/1302 Pages) FREESCALE

1103 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

19-25

RxBD read latency

(duration threshold)

Ref:55

Times RxBD read latency exceeds threshold (threshold

event)

Start: request asserted

Stop: data acknowledge received

TxBD read latency

(duration threshold)

Ref:56

Times TxBD read latency exceeds threshold (threshold

event)

Start: request asserted

Stop: data acknowledge received

RxBD write latency

(duration threshold)

Ref:57

Times RxBD write response latency exceeds threshold

(threshold event). Only for writes that require a response

Start: request asserted

Stop: End of Transaction received

TxBD write latency

(duration threshold)

Ref:58

Times that TxBD write response latency exceeds threshold

(threshold event). Only for writes that require a response

Start: request asserted

Stop: End of Transaction received

Tx data read latency

(duration threshold)

Ref:59

Data read response latency exceeds threshold (threshold

event)

Start: request asserted

Stop: Data acknowledge received

Data beats

C7:49

—

Read data beats

C8:47

—

Rx frame interrupts

C1:50

BD receive interrupt is set on a last BD

Tx frame interrupts

C3:54

BD transmit interrupt is set on a BD with L = 1

Rx frame processing

Ref:60

Receive frame processing exceeds threshold (threshold

event)

Start: Open first BD

Stop: Close last BD

Local Bus Events

Bank 1 hits (chip-select)

C1:51

—

Bank 2 hits (chip-select)

C2:56

—

Bank 3 hits (chip-select)

C3:55

—

Bank 4 hits (chip-select)

C4:54

—

Bank 5 hits (chip-select)

C5:48

—

Bank 6 hits (chip-select)

C6:53

—

Bank 7 hits (chip-select)

C7:50

—

Bank 8 hits (chip-select)

C8:50

—

Requests granted to ECM port

C2:57

—

Cycles atomic reservation for ECM port

is enabled

C4:55

Table 19-10. Performance Monitor Events (continued)

Event Counted

Number

Description of Event Counted

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