ADC32RF55 datasheet(45/126 Pages) TI

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7.3.2 Sampling Clock Input

The internal sampling clock path was designed for lowest residual phase noise contribution. The sampling clock

circuitry requires a dedicated low noise power supply for best performance. The internal residual clock phase

noise is also sensitive to clock amplitude. For best performance, the clock amplitude should be larger than 1

Vpp. The phase noise ideally improves by 3 dB per 2x averaging, however at higher input frequenices the clock

path contribution reduces the improvement.

Table 7-7. Internal Aperture Clock Phase Noise

(FS = 3 Gsps, VIN = 1 Vpp)

Frequency Offset (MHz)

Amplitude (dBc/Hz)

0.001

-117

0.01

-127

0.1

-137

-147

-154

250

-160

The clock input and ADC sampling circuitry also have an amplitude noise component which modulates on to

the sampled input signal. Unlike phase noise, the amplitude noise doesn't scale with input frequency, it is only

affected by the sampling reset switch as shown in Figure 7-10 and Figure 7-11. This noise component can

dominate the close in noise performance at lower input frequencies.

Frequency (MHz)

0.0001

0.001

0.01

0.1

-160

-150

-140

-130

-120

-110

-100

-90

FIN = 110 MHz, RS_SW DIS

FIN = 710 MHz, RS_SW DIS

FIN = 910 MHz, RS_SW DIS

FIN = 110 MHz, RS_SW EN

FIN = 710 MHz, RS_SW EN

FIN = 910 MHz, RS_SW EN

Figure 7-10. Amplitude Noise vs Input Frequency

Input Frequency (MHz)

100

1000

3000

-150

-145

-140

-135

-130

-125

-120

-115

Phase Noise RS_SW DIS

Phase Noise RS_SW EN

Amplitude Noise RS_SW DIS

Amplitude Noise RS_SW EN

Figure 7-11. Amplitude and Phase noise at 10 kHz

offset vs Input Frequency

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ADC32RF54, ADC32RF55

SBAS500A – JUNE 2022 – REVISED DECEMBER 2022

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