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ADC32RF55 Datasheet(PDF) 95 Page - Texas Instruments |
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ADC32RF55 Datasheet(HTML) 95 Page - Texas Instruments |
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95 / 126 page ![]() Figure 7-84. Register 0x180 (DDCA/B page) 7 6 5 4 3 2 1 0 0 0 DDC PDN DDC DITH PDN REAL DDC DB/QB DDC 0 NCO MODE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-92. Register 0x180 Field Descriptions Bit Field Type Reset Description 7-6 0 R/W 0 Must write 0 5 DDC PDN R/W 0 This bit powers down the DDC mixer and NCO 0: DDC block enabled 1: DDC block powered down 4 DDC DITH PDN R/W 0 This bit powers down the dither in the DDC digital block 0: DDC dither enabled 1: DDC dither powered down 3 REAL DDC R/W 0 Set this bit to 1 in real decimation mode to disable the NCO. 0: Complex Decimation 1: Real Decimation 2 DB/QB DDC R/W 0 This register splits the NCOs for dual or quad band operation. 0: Dual Band 1: Quad Band 1 0 R/W 0 Must write 0 0 NCO MODE R/W 0 This register selects phase coherent or phase continuous operation of the NCO. 0: Phase continuous 1: Phase coherent Figure 7-85. Register 0x181 (DDCA/B page) 7 6 5 4 3 2 1 0 0 0 LOAD NCO 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-93. Register 0x181 Field Descriptions Bit Field Type Reset Description 7-6 0 R/W 0 Must write 0 5-4 LOAD NCO R/W 00 This register loads all the NCO frequencies from the memory to the NCOs. To update the NCO this register has to be set to 3 and back to 0 as shown in Table 7-94. 3-0 0 R/W 0 Must write 0 Table 7-94. NCO frequency programming example ADDR DATA DESCRIPTION 0x105 0x4E Frequency = 920 MHz with FS = 3 GSPS 86,318,992,857,935 = 0x4E81B4E81BE4 where the MSB goes to address 0x105 and the LSB to 0x100. 0x104 0x81 0x103 0xB4 0x102 0xE8 0x101 0x1B 0x100 0x4E 0x181 0x00 Load and update all NCO frequencies 0x181 0x30 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 95 Product Folder Links: ADC32RF54 ADC32RF55 |
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