ADC32RF55 datasheet(70/126 Pages) TI

70 / 126 page

7.3.7 SERDES Output MUX

The SERDES output block contains one digital mux per SERDES output lane with a 3-bit register. This allows

routing any of the 8 digital streams to any output serdes transmitter as shown in the example in Figure 7-43. The

MUX can be used to reorder lanes as well as duplicate lane outputs (for example in LMFS = 1-4-8-1 mode the

same output stream could be duplicated on all 8 lanes).

MUX

Stream 0

Stream 1

Stream 6

Stream 7

DOUT0...7P/M

SPI:

Lane x mux

select

Figure 7-43. SERDES output mux for DOUT0

By default after power, the active SERDES lanes start on lane DOUT0 as shown for the complex decimation

dual band example in Table 7-43. After power up, the output is transmitted on lanes DOUT0..3. Using the

digital output muxes, the output data for channel B is shifted from lanes DOUT2,3 to DOUT4,5. All SERDES

transmitters are powered up and enabled by default. After configuring the output mux unused lanes can be

powered down to save power consumption.

Table 7-43. JESD Sample Frame Assembly: Complex Decimation - Dual Band with LMFS = 4841

OUTPUT

LANE

Default

Using MUX

DOUT0

A1I0 [15:8]

A1I0 [7:0]

A1Q0 [15:8]

A1Q0 [7:0]

A1I0 [15:8]

A1I0 [7:0]

A1Q0 [15:8]

A1Q0 [7:0]

DOUT1

A2I0 [15:8]

A2I0 [7:0]

A2Q0 [15:8]

A2Q0 [7:0]

A2I0 [15:8]

A2I0 [7:0]

A2Q0 [15:8]

A2Q0 [7:0]

DOUT2

B1I0 [15:8]

B1I0 [7:0]

B1Q0 [15:8]

B1Q0 [7:0]

DOUT3

B2I0 [15:8]

B2I0 [7:0]

B2Q0 [15:8]

B2Q0 [7:0]

DOUT4

B1I0 [15:8]

B1I0 [7:0]

B1Q0 [15:8]

B1Q0 [7:0]

DOUT5

B2I0 [15:8]

B2I0 [7:0]

B2Q0 [15:8]

B2Q0 [7:0]

DOUT6

DOUT7

Table 7-44 shows the register writes to shift the output lanes from default as illustrated in Table 7-43.

Table 7-44. Example register writes to shift the output serdes lanes using the SERDES Output MUX

ADDR

DATA

DESCRIPTION

0x05

0x04

Select JESD page

0x81

0x54

Select internal JESD streams 4 and 5 to lanes DOUT2 and DOUT3

0x82

0x32

Select internal JESD streams 2 and 3 to lanes DOUT4 and DOUT5

ADC32RF54, ADC32RF55

SBAS500A – JUNE 2022 – REVISED DECEMBER 2022

www.ti.com

Submit Document Feedback

Product Folder Links: ADC32RF54 ADC32RF55

ADC32RF55 Datasheet(PDF) 70 Page - Texas Instruments

ADC32RF55 Datasheet(HTML) 70 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL