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ADC32RF55 Datasheet(PDF) 46 Page - Texas Instruments |
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ADC32RF55 Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 126 page ![]() The internal aperture jitter is also dependent on the amplitude of the external clock input signal. Figure 7-12 and Figure 7-13 show the expected SNR performance with dither on/off across clock amplitude (FS = 2.6 GSPS). Figure 7-12. SNR vs Clock Amplitude (Dither OFF) Figure 7-13. SNR vs Clock Amplitude (Dither ON) The sampling clock input is internally terminated to 100 Ω differentially and provides a return loss better than 10 dB at 3 GHz (see Figure 7-14). The clock input consists of a single clock input buffer followed by a dedicated clock buffer for ADCA1/2 as well as ADCB1/2. When averaging multiple ADCs, there are some close in clock buffer noise which is correlated; and thus, does not improve with averaging. CLKP CLKM To ADCA1/2 To ADCB1/2 5 k V CM 5 k 100 V CM Buffer Figure 7-14. Internal Clock Input Routing ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com 46 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADC32RF54 ADC32RF55 |
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