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ADC32RF55 Datasheet(PDF) 98 Page - Texas Instruments |
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ADC32RF55 Datasheet(HTML) 98 Page - Texas Instruments |
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98 / 126 page ![]() Figure 7-92. Register 0xA8 (ANALOG page) 7 6 5 4 3 2 1 0 0 DITH AMP1 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-101. Register 0xA8 Field Descriptions Bit Field Type Reset Description 7 0 R/W 0 Must write 0 6-3 DITH AMP1 R/W 0000 This register sets dither amplitude coarse gain. There are two recommended settings: 0000: Amplitude = 0 0011: Amplitude = 3 Here is a list of all the settings: 0000: Amplitude = 0 (smallest) 0001: Amplitude = 1 ... 1110: Amplitude = 14 1111: Amplitude = 15 (largest) 2-0 0 R/W 0 Must write 0 Figure 7-93. Register 0xAF (ANALOG page) 7 6 5 4 3 2 1 0 DITHER DIS 0 0 1 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-102. Register 0xAF Field Descriptions Bit Field Type Reset Description 7 DITHER DIS R/W 0 This register disables internal dither. 0: Dither enabled 1: Dither disabled 6-5 0 R/W 0 Must write 0 4 1 R/W 0 Must write 1 3-0 0 R/W 0 Must write 0 Figure 7-94. Register 0xB1 (ANALOG page) 7 6 5 4 3 2 1 0 DITHER DIVIDER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-103. Register 0xB1 Field Descriptions Bit Field Type Reset Description 7-0 DITHER DIVIDER R/W 0 This register sets the dither divider frequency. SPI write is actual -1. For example a divider of 48 is 47 (0x2F). 0x00 (default) is a divide /50 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com 98 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADC32RF54 ADC32RF55 |
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