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7.3.8 Test Pattern

The ADC32RF5x provides two different options to output test patterns instead of the actual output data of the

ADC in order to simplify the serial interface and system debug of the JESD204B digital interface link. The output

data path is shown in \.

Transport Layer Test

Pattern

Data Mapping

Frame Construction

Scrambler

1+x

14+x15

8b/10b

encoding

Link Layer Test Pattern

Serializer

ADC Section

Transport Layer

Link Layer

PHY Layer

Digital Block

ADC

Decimation

Filter Block

Figure 7-44. Test Pattern Options

The available test patterns in each block are described in Table 7-45. Both test pattern blocks replace output

data from the digital block, and not from the ADC; therefore, it is available in decimation or decimation bypass

mode. The test patterns are synchronized with the SYSREF signal.

Table 7-45. Test Pattern Overview

TEST PATTERN LOCATION

TYPE

8b/10b encoded

TRANSPORT LAYER

CUSTOM PATTERN

Yes

JESD

0x05 0x04

0x2E, D0

TOGGLE 1010 PATTERN

Yes

0x2E, D1

RAMP PATTERN

Yes

0x2E, D2

LINK LAYER

JESD204B TEST PATTERNS

Depends

0x2D, D2-D0

PRBS PATTERN (27.. 231)

0x2F, D6-D4

The RAMP pattern provides two different output options. Internally each ADC data bus consists of parallel data

streams (1 stream per serdes lane). The RAMP pattern is generated for each stream and a different starting

value can be set for each stream. By default, the starting values are 0. For example, a LMFS mode using 4

lanes/ADC would show a slow ramp which increments once every 4 clock cycles with starting values set to 0 and

ramp increment = 1. Also, a RAMP pattern which increments every clock cycle can be set using different starting

values (such as 0, 1, 2, 3) for the 4 streams/lanes and setting the RAMP increment to 4. The follow table shows

how to enable the RAMP test pattern.

Table 7-46. RAMP Test Pattern

ADDR

DATA

DESCRIPTION

0x05

0x04

Select JESD page

0x32

0x01

Set lane DOUT1 starting value = 1

0x34

0x02

Set lane DOUT2 starting value = 2

0x36

0x03

Set lane DOUT3 starting value = 3

0x42

0x01

Set lane DOUT5 starting value = 1

0x44

0x02

Set lane DOUT6 starting value = 2

0x46

0x03

Set lane DOUT7 starting value = 3

0x2E

0x34

Enable RAMP pattern, RAMP increment = 4

7.3.8.1 Transport Layer

The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the

LMFS parameters. Tail bits or 0's are added when needed. Alternatively, test patterns can be substituted instead

of the ADC data with the JESD frame, as shown in Table 7-45.

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ADC32RF54, ADC32RF55

SBAS500A – JUNE 2022 – REVISED DECEMBER 2022

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