ADC32RF55 datasheet(73/126 Pages) TI

73 / 126 page

7.4 Device Functional Modes

The device offers two different operating modes: bypass mode (1x AVG) and digital averaging (2x/4x AVG). Both

operating modes use the same digital back end and JESD204B output configurations.

7.4.1 Digital Averaging

The ADC32RF5x provides a total of eight internal single core 3.0 Gsps ADCs. Normal bypass mode uses only

two ADC cores (one ADC per channel). However, the additional six ADCs can be used to trade off further noise

density improvement against additional power consumption. Figure 7-45 shows the internal block diagrams for

the digital averaging modes. In averaging mode the output resolution is increased to 16-bit to avoid quantization

noise limitation.

In 2x averaging mode (left), one external input is connected to the INx1 input where two ADC cores internally

average the input signal. In 4x averaging (right), the signal has to be split externally and connected to both the

INx1 and INx2 inputs where four ADC cores internally average the signal.

INx1P/M

50 ,

100

ADC

INx1P/M

50 ,

100

ADC

INx2P/M

50 ,

100

ADC

External

Figure 7-45. Internal digital averaging (left: 2x, right: 4x)

Table 7-48 provides a trade-off comparison of the 3 different averaging mode options vs the default, non-

averaged mode.

Table 7-48. Digital Averaging vs Full Power Input Bandwidth (–3 dB)

# of ADCs

averaged

ADC inputs used for

averaging

Input Bandwidth

(-3 dB)

Selected differential

input termination

Noise density

Power/ch (W)

Default

INx1

2.75 GHz

100 Ω

-156 dBFS/Hz

~2.1

INx1

2.75 GHz

100 Ω

-158 dBFS/Hz

~2.6

INx1, INx2

2.1 GHz

100 Ω

-160 dBFS/Hz

~3.5

Digital averaging improves decorrelated noise contributions by 3 dB per 2x AVG (ideal) while correlated

noise does not improve with averaging. Some of the dominant noise sources are correlated, that is, clock

jitter (external or first clock input buffer), or power supply noise. While others (such as, ADC thermal noise,

clock distribution buffers) are decorrelated. Table 7-49 illustrates a performance example comparison across

averaging options.

SNR: When operating close to ADC fullscale, some of the SNR limitation is due to jitter and hence the SNR

improvement will not reach 3 dB (2x AVG) or 6 dB (4x AVG). As the input fullscale is reduced, the clock jitter

contribution to SNR becomes less and the SNR improvement is approaching the ideal 3 dB per 2x AVG. The

same phenomenon can be observed when using digital decimation. As the decimation factor increases, the

close-in (correlated noise) becomes the more dominating noise unless the input signal amplitude is reduced.

SFDR: The amplitude of low order harmonics (HD2-HD5) and IMD3 typically is similar across ADCs; thus, the

improvement with averaging is small.

www.ti.com

ADC32RF54, ADC32RF55

SBAS500A – JUNE 2022 – REVISED DECEMBER 2022

Submit Document Feedback

Product Folder Links: ADC32RF54 ADC32RF55

ADC32RF55 Datasheet(PDF) 73 Page - Texas Instruments

ADC32RF55 Datasheet(HTML) 73 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL