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ATA663201 Datasheet(PDF) 12 Page - Microchip Technology |
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ATA663201 Datasheet(HTML) 12 Page - Microchip Technology |
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12 / 36 page ![]() ATA663201/03/31/54 DS20006075D-page 12 2018-2021 Microchip Technology Inc. 1.6 Pin Descriptions The descriptions of the pins are listed in Table 1-4. 1.6.1 OUTPUT PIN (RXD) (SBC ONLY) In Normal mode this pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is indicated by a high level at RXD; LIN low (dominant state) is indicated by a low level at RXD. The output is a push-pull stage switching between VCC and GND. The AC characteristics are measured by an external load capacitor of 20 pF. In Silent mode, the RXD output switches to high. 1.6.2 ENABLE INPUT PIN (EN) (SBC ONLY) The enable input pin controls the operating mode of the device. If EN is high, the circuit is in Normal mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/85 mA output capability. If EN is switched to low while TXD is still high, the device is forced to Silent mode. No data transmission is then possible, and current consumption is reduced to IVSsilent typical 47 µA. The VCC regulator retains its full functionality. If EN is switched to low while TXD is low, the device is forced to Sleep mode. No data transmission is possible and the voltage regulator is switched off. The EN pin provides a pull-down resistor to force the transceiver into Recessive mode if EN is disconnected. 1.6.3 UNDERVOLTAGE RESET OUTPUT (NRES) If the VCC voltage falls below the undervoltage detection threshold VVCC_th_uv_down, NRES switches to low after tres_f. The NRES stays low even if VVCC = 0V because NRES is internally driven from the VS voltage. If the VS voltage ramps down, NRES stays low until VVS < 1.5V and then becomes highly impedant. The implemented undervoltage delay keeps NRES low for tReset = 4 ms after VVCC reaches its nominal value. TABLE 1-4: PIN FUNCTION TABLE ATA663201 ATA663203 ATA663231 ATA663254 Symbol Description 3 x 3 VDFN 3 x 3 VDFN 3 x 3 VDFN 3x 3 VDFN/ SOIC — — 1 1 RXD Receive Data Output — — 2 2 EN Enables Normal Mode if the Input is High 3 3 3 3 NRES VCC Undervoltage Output, Open Drain, Low at Reset — — 4 4 TXD Transmit Data Input 5 5 5 5 GND Ground 6 6 6 6 LIN LIN Bus Line Input/Output — — 7 7 VS Supply Voltage 8 8 8 8 VCC Output Voltage Regulator 3.3V/5V/85 mA 1,2,4,6 1,2,4,6 — — NC Not Connected EP EP EP EP EP Exposed Thermal Pad, Internally Connected to the GND pin (Note 1) Note 1: Only for the VDFN package. |
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