ADP3182

Rev. 0 | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTION

ADP3182

TOP VIEW

(Not to Scale)

VCC

FBRTN

FB

COMP

PWRGD

EN

DELAY

RT

RAMPADJ

ILIMIT

PWM1

PWM2

PWM3

SW1

SW2

SW3

GND

CSCOMP

CSSUM

CSREF

1

2

3

20

19

18

4

8

10

5

6

7

13

16

15

14

9

11

12

17

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VCC

Supply Voltage for the Device.

2

FBRTN

Feedback Return. Voltage error amplifier reference for remote sensing of the output voltage.

3

FB

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor divider

between the output and FBRTN connected to this pin sets the output voltage point. This pin is also the reference

point for the power good and crowbar comparators.

4

COMP

Error Amplifier Output and Compensation Point.

5

PWRGD

Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating

range.

6

EN

Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.

7

DELAY

Soft Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected

between this pin and GND sets the soft start, ramp-up time and the overcurrent latch-off delay time.

8

RT

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator

frequency of the device.

9

RAMPADJ

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.

10

ILIMIT

Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit threshold

of the converter. This pin is actively pulled low when the ADP3182’s EN input is low, or when VCC is below its

UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low.

11

CSREF

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense

amplifier. This pin should be connected to the common point of the output inductors.

12

CSSUM

Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor

currents together to measure the total output current.

13

CSCOMP

Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determines the gain of the

current sense amplifier.

14

GND

Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

15 to 17

SW3 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases

should be left open.

18 to 20

PWM3 to

PMW1

Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the

ADP3418. Connecting the PWM3 output to GND causes that phase to turn off, allowing the ADP3182 to operate

as a 1- or 2-phase controller.