ADP3182 datasheet(14/20 Pages) AD

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ADP3182

Rev. 0 | Page 14 of 20

APPLICATIONS

The design parameters for the typical high current point-of-

load dc/dc buck converter shown in Figure 9 are as follows:

•

Input voltage (VIN) = 12 V

•

VID setting voltage (VOUT) = 1.8 V

•

Duty cycle (D) = 0.15

•

Output current IO = 55 A

•

Maximum output current (ILIM) = 110 A

•

Number of phases (n) = 3

•

Switching frequency per phase (fSW) = 250 kHz

SETTING THE CLOCK FREQUENCY

The ADP3182 uses a fixed-frequency control architecture. The

frequency is set by an external timing resistor (RT). The clock

frequency and the number of phases determine the switching

frequency per phase, which relates directly to switching losses

and the sizes of the inductors and the input and output

capacitors. With n = 3 for three phases, a clock frequency of

750 kHz sets the switching frequency (fSW) of each phase to

250 kHz, which represents a practical trade-off between the

switching losses and the sizes of the output filter components.

Equation 1 shows that to achieve a 750 kHz oscillator frequency,

the correct value for RT is 256 kΩ. Alternatively, the value for RT

can be calculated using

kΩ

4.7

−

(1)

kΩ

256

kΩ

4.7

kHz

250

−

where 4.7 pF and 27 kΩ are internal IC component values. For

good initial accuracy and frequency stability, a 1% resistor is

recommended. The closest standard 1% value for this design is

258 kΩ.

SOFT START AND CURRENT LIMIT LATCH-OFF

DELAY TIME

Because the soft start and current limit latch-off delay functions

share the DELAY pin, these two parameters must be considered

together. The first step is to set CDLY for the soft start ramp. This

ramp is generated with a 20 µA internal current source. The

value of RDLY has a second-order impact on the soft start time

because it sinks part of the current source to ground. However,

as long as RDLY is kept greater than 200 kΩ, this effect is minor.

The value for CDLY can be approximated using

OUT

DLY

OUT

DLY

⎟

⎠

⎞

⎜

⎝

⎛

−

μA

(2)

where:

tSS

is the desired soft start time.

Assuming an RDLY of 390 kΩ and a desired soft start time of 3

ms, CDLY is 36 nF.

The closest standard value for CDLY is 39 nF.

Once CDLY is chosen, RDLY can be calculated for the current limit

latch-off time using

DLY

DELAY

DLY

(3)

If the result for RDLY is less than 200 kΩ, a smaller soft start time

should be considered by recalculating the equation for CDLY, or a

longer latch-off time should be used. RDLY should never be less

than 200 kΩ. In this example, a delay time of 9 ms results in

RDLY = 452 kΩ. The closest standard 5% value is 470 kΩ.

INDUCTOR SELECTION

The amount of inductance determines the ripple current in the

inductor. Less inductance leads to more ripple current, which

increases the output ripple voltage and conduction losses in the

MOSFETs, but allows using smaller inductors and, for a

specified peak- peak transient deviation, less total output

capacitance. Conversely, a higher inductance means lower

ripple current and reduced conduction losses, but requires

larger inductors and more output capacitance for the same

peak-peak transient deviation. In any multiphase converter, a

practical value for the peak-peak inductor ripple current is less

than 50% of the maximum dc current in the same inductor.

Equation 4 shows the relationship between the inductance,

oscillator frequency, and peak-peak ripple current in the

inductor.

Equation 5 can be used to determine the minimum inductance

based on a given output ripple voltage.

(

)

OUT

−

(4)

(

)

(

)

RIPPLE

OUT

−

≥

(5)

where:

RX is ESR of output bulk capacitors.

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