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ADP3182 Datasheet(PDF) 16 Page - Analog Devices |
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ADP3182 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 20 page ![]() ADP3182 Rev. 0 | Page 16 of 20 The closest standard 1% value for RPH(X) is 140 kΩ. Next, use Equation 7 to solve for CCS. nF 29 . 4 Ω k 100 Ω m 4 . 1 nH 600 ≥ × ≥ CS C Choose the closest standard value that is greater than the result given by Equation 7. This example uses a CCS value of 5.6 nF. OUTPUT VOLTAGE ADP3182 has an internal FBRTN voltage reference VREF of 800 mV. The output voltage can be set up using a voltage divider made up of resistors RB1 and RB2: REF B B B OUT V R R R V × + = 1 2 1 (8) Rearranging Equation 8 to solve for RB2 using the ADP3182 with an internal FB voltage of 800 mV and assuming a 1%, 1 kΩ resistor for RB1 yields Ω = Ω × ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − = × ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ − = k 25 . 1 k 1 1 V 8 . 0 V 8 . 1 1 1 2 B REF OUT B R V V R The closest standard 1% resistor value for RB2 is 1.24 kΩ. POWER MOSFETS For this example, one high-side, N-channel power MOSFET and two low-side, N-channel power MOSFETs per phase have been selected. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3418) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3182, currents are balanced between phases, thus the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and the average total output current (IO): () ( ) SF DS SF R SF O SF R n I n n I D P × ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × + ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × − = 2 2 12 1 1 (9) Knowing the maximum output current and the maximum allowed power dissipation, one can determine the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50°C, a safe limit for PSF is 1 W to 1.5 W at 120°C junction temperature. Therefore, for this example, RDS(SF) (per MOSFET) < 7.5 mΩ. This RDS(SF) is also at a junction temperature of about 120°C, so one must account for this when making this selection. This example uses a lower-side MOSFET with 4.8 mΩ at 120°C. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of feedback to input must be small (less than 10% is recom- mended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3418). The output impedance of the driver is approximately 2 Ω, and the typical MOSFET input gate resistances are about 1 Ω to 2 Ω; therefore, one should adhere to a total gate capacitance of less than 6000 pF. Because there are two MOSFETs in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000 pF. The high-side (main) MOSFET must handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET: () ISS MF G MF O CC SW MF S C n n R n I V f P × × × × × × = 2 (10) where: nMF is the total number of main MOSFETs. RG is the total gate resistance (2 Ω for the ADP3418 and about 1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω). CISS is the input capacitance of the main MOSFET. Note that adding more main MOSFETs (nMF) does not help the switching loss per MOSFET because the additional gate capacitance slows switching. The most efficient way to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following equation: () ( ) MF DS MF R MF MF C R n I n n D P × ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × × + ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × = 2 2 O 12 1 I (11) where: RDS(MF) is the on resistance of the MOSFET. Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but faster devices usually have higher on resistance. Select a device that meets the total power dissipation |
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