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ADP3182

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(about 1.5 W for a single D-PAK) when combining the

switching and conduction losses.

For this example, an NTD40N03L was selected as the main

MOSFET (three total; nMF = 3), with a CISS = 584 pF (max) and

RDS(MF) = 19 mΩ (max at TJ = 120°C), and an NTD110N02L was

selected as the synchronous MOSFET (three total; nSF = 3), with

CISS = 2710 pF (max) and RDS(SF) = 4.8 mΩ (max at TJ = 120°C).

The synchronous MOSFET CISS is less than 3000 pF, satisfying

that requirement. Solving for the power dissipation per MOSFET

at IO = 55 A and IR = 6.6 A yields 894 mW for each synchronous

MOSFET and 1.16 W for each main MOSFET. These numbers

comply with the guideline to limit the power dissipation to

around 1 W per MOSFET.

One last thing to consider is the power dissipation in the driver

for each phase. This is best described in terms of the QG for the

MOSFETs and is given by the following equation:

()

GSF

GMF

DRV

⎥

⎦

⎤

⎢

⎣

⎡

(12)

where:

QGMF is the total gate charge for each main MOSFET.

QGSF is the total gate charge for each synchronous MOSFET.

Also shown is the standby dissipation factor (ICC × VCC) for the

driver. For the ADP3418, the maximum dissipation should be

less than 400 mW. In this example, with ICC = 7 mA, QGMF =

9 nC, and QGSF = 46 nC, there is 165 mW in each driver, which

is below the 400 mW dissipation limit. See the ADP3418 data

sheet for more details.

RAMP RESISTOR SELECTION

The ramp resistor (RR) is used for setting the size of the internal

PWM ramp. The value of this resistor is chosen to provide the

best combination of thermal balance, stability, and transient

response. The following expression is used to determine the

optimum value:

kΩ

333

0.2

)

)(

(

(13)

where:

AR is the internal ramp amplifier gain.

AD is the current balancing amplifier gain.

RDS(ON)(SF) is the total low-side MOSFET on resistance.

CR is the internal ramp capacitor value.

The closest standard 1% resistor value is 332 kΩ.

The internal ramp voltage magnitude can be calculated by using

(

)

()

737

kHz

332

0.1

0.2

−

OUT

(14)

The size of the internal ramp can be made larger or smaller. If it

is made larger, stability and transient response improve, but

thermal balance degrades. Likewise, if the ramp is made

smaller, thermal balance improves but transient response and

stability degrade. The factor of three in the denominator of

Equation 13 sets a ramp size with optimal balance for good

stability, transient response, and thermal balance.

CURRENT LIMIT SETPOINT

To select the current limit setpoint, first find the resistor value

for RLIM. The current limit threshold for the ADP3182 is set

with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/µA

(ALIM). RLIM can be found using

DRPMAX

LIM

(15)

For values of RLIM greater than 500 kΩ, the current limit may be

lower than expected and therefore necessitate some adjustment of

RLIM. Here, ILIM is the average current limit for the output of the

supply. In this example, using the VDRPMAX value of 110 mV from

Equations 6 and 7 and choosing a peak current limit of 110 A

for ILIM results in RLIM = 284 kΩ, for which 287 kΩ is chosen as

the nearest 1% value.

The limit of the per phase current limit described earlier is

determined by

()

MAX

BIAS

MAX

COMP

PHLIM

−

≅

(16)

FEEDBACK LOOP COMPENSATION DESIGN

Optimized compensation of the ADP3182 allows the best

possible response of the regulator’s output to a load change. The

basis for determining the optimum compensation is to make

the regulator and output decoupling appear as an output

impedance that is entirely resistive over the widest possible

frequency range, including dc.

With the multimode feedback structure of the ADP3182, the

feedback compensation must be set so that the converter’s

output impedance, working in parallel with the output

decoupling, will meet this goal. One will need to compensate for

the several poles and zeros created by the output inductor and

decoupling capacitors (output filter).

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