ADP3182 datasheet(19/20 Pages) AD

19 / 20 page

ADP3182

Rev. 0 | Page 19 of 20

()

CS2

CS1

−

(22)

CS1

CS2

−

(23)

Calculate RTH = rTH × RCS, then select the closest value of

thermistor available. Also, compute a scaling factor k based

on the ratio of the actual thermistor value used relative to

the computed one:

(

)

()

CALCULATED

ACTUAL

k =

(24)

Calculate values for RCS1 and RCS2 using

CS1

(25)

()

(

)

(

)

CS2

−

(26)

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal

performance of a switching regulator in a PC system.

General Recommendations

For good results, a PCB with at least four layers is recommended.

This should allow the needed versatility for control circuitry

interconnections with optimal placement, power planes for

ground, input and output power, and wide interconnection

traces in the remainder of the power delivery current paths.

Keep in mind that each square unit of 1 ounce copper trace

has a resistance of ~0.53 mΩ at room temperature.

When high currents must be routed between PCB layers, vias

should be used liberally to create several parallel current paths

so that the resistance and inductance introduced by these current

paths is minimized and the via current rating is not exceeded.

If critical signal lines (including the output voltage sense lines of

the ADP3182) must cross through power circuitry, a signal

ground plane should be interposed between those signal lines

and the traces of the power circuitry. This serves as a shield to

minimize noise injection into the signals at the expense of

making the signal ground a bit noisier.

An analog ground plane should be used around and under the

ADP3182 as a reference for the components associated with the

controller. This plane should be tied to the nearest output de-

coupling capacitor ground, but it should not be tied to any other

power circuitry to prevent power currents from flowing in it.

The components around the ADP3182 should be located close

to the controller with short traces. The most important traces to

keep short and away from other traces are the FB and CSSUM

pins. The output capacitors should be connected as close as

possible to the load or connector. If the load is distributed, the

capacitors should also be distributed and generally be in pro-

portion to where the load tends to be more dynamic. Avoid

crossing any signal lines over the switching power path loop,

described in the following section.

Power Circuitry Recommendations

To minimize radiated switching noise energy (i.e., EMI) and

conduction losses in the board, the switching power path should

be routed on the PCB to encompass the shortest possible length.

Failure to take proper precautions often results in EMI problems

for the entire PC system as well as noise-related operational

problems in the power-converter control circuitry. The switching

power path is the loop formed by the current path through the

input capacitors and the power MOSFETs, including all inter-

connecting PCB traces and planes. Using short and wide

interconnection traces is especially critical in this path for two

reasons: it minimizes the inductance in the switching loop,

which can cause high energy ringing, and it accommodates the

high current demand with minimal voltage loss.

When a power-dissipating component, for example, a power

MOSFET, is soldered to a PCB, the liberal use of vias, both

directly on the mounting pad and immediately surrounding it,

is recommended. Two important reasons for this are improved

current rating through the vias and improved thermal

performance from vias that extend to the opposite side of the

PCB, where a plane can more readily transfer the heat to the air.

To optimize thermal dissipation, make a mirror image of the

pads in use to heat sink the MOSFETs on the opposite side of

the PCB. To further improve thermal performance, use the

largest possible pad area.

The output power path should also be routed to encompass a

short distance. The output power path is formed by the current

path through the inductor, the output capacitors, and the load.

For best EMI containment, a solid power ground plane should

be used as one of the inner layers, extending fully under all the

power components.

Signal Circuitry Recommendations

The output voltage is sensed and regulated between the FB pin

and the FBRTN pin, which connect to the signal ground at the

load. To avoid differential mode noise pickup in the sensed signal,

the loop area should be small. Therefore, the FB and FBRTN

traces should be routed adjacent to each other on top of the

power ground plane back to the controller. The feedback traces

from the switch nodes should be connected as close as possible

to the inductor. The CSREF signal should be connected to the

output voltage at the nearest inductor to the controller.

ADP3182 Datasheet(PDF) 19 Page - Analog Devices

ADP3182 Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL