ADP3182 datasheet(11/20 Pages) AD

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ADP3182

Rev. 0 | Page 11 of 20

After the limit is reached, the 3 V pull-up on the DELAY pin is

disconnected, and the external delay capacitor is discharged

through the external resistor. A comparator monitors the DELAY

voltage and shuts off the controller when the voltage drops

below 1.8 V. The current limit latch-off delay time is therefore

set by the RC time constant discharging from 3 V to 1.8 V.

Typical overcurrent latch-off waveforms are shown in Figure 7.

Because the controller continues to cycle the phases during the

latch-off delay time, the controller returns to normal operation

if the short is removed before the 1.8 V threshold is reached.

The recovery characteristic depends on the state of PWRGD. If

the output voltage is within the PWRGD window, the controller

resumes normal operation. However, if a short circuit has

caused the output voltage to drop below the PWRGD threshold,

a soft start cycle is initiated.

The latch-off function can be reset by either removing and

reapplying VCC to the ADP3182, or by pulling the EN pin low

for a short time. To disable the short-circuit latch-off function,

the external resistor to ground should be left open, and a high-

value (>1 MΩ) resistor should be connected from DELAY to

VCC. This prevents the DELAY capacitor from discharging, so

the 1.8 V threshold is never reached. The resistor has an impact

on the soft start time because the current through it adds to the

internal 20 µA current source.

During start-up when the output voltage is below 200 mV, a

secondary current limit is active. This is necessary because the

voltage swing of CSCOMP cannot go below ground. This

secondary current limit controls the internal COMP voltage to

the PWM comparators to 2 V. This limits the voltage drop

across the low-side MOSFETs through the current balance

circuitry.

An inherent per phase current limit protects individual phases

if one or more phases stop functioning because of a faulty

component. This limit is based on the maximum normal mode

COMP voltage.

POWER GOOD MONITORING

The power good comparator monitors the output voltage via the

FB pin. The PWRGD pin is an open-drain output whose high

level (when connected to a pull-up resistor) indicates that the

output voltage is within the nominal limits specified in the

electrical table. PWRGD goes low if the output voltage is

outside this specified range or the EN pin is pulled low. Figure 8

shows the PWRGD output response when the input power is

removed from the regulator.

Figure 7. Overcurrent Latch-Off Waveforms

Channel 1: CSREF, Channel 2: COMP,

Channel 3: Phase 1 Switch Node, Channel 4: DELAY

Figure 8. Shutdown Waveforms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: PWRGD, Channel 4: COMP

OUTPUT CROWBAR

As part of the protection for the load and output components of

the supply, the PWM outputs are driven low (turning on the

low-side MOSFETs) when the output voltage exceeds the upper

crowbar threshold. This crowbar action stops once the output

voltage falls below the release threshold of approximately 650 mV.

Turning on the low-side MOSFETs pulls down the output as the

reverse current builds up in the inductors. If the output over-

voltage is due to a short in the high-side MOSFET, this action

limits the current of the input supply or blows the fuse to

protect the microprocessor from being destroyed.

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