ADP3182 datasheet(9/20 Pages) AD

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ADP3182

Rev. 0 | Page 9 of 20

THEORY OF OPERATION

The ADP3182 combines a multimode, fixed frequency PWM

control with multiphase logic outputs for use in 1-, 2-, and

3-phase, synchronous, buck, point-of-load supply power

converters. Multiphase operation is important for producing the

high currents and low voltages demanded by auxiliary supplies

in desktop computers, workstations, and servers. Handling the

high currents in a single-phase converter would place high

thermal demands on the components in the system, such as the

inductors and MOSFETs.

The multimode control of the ADP3182 ensures a stable, high

performance topology for

•

Balancing currents and thermals between phases

•

High speed response at the lowest possible switching

frequency and output decoupling

•

Minimizing thermal switching losses due to lower

frequency operation

•

Tight regulation and accuracy

•

Reduced output ripple due to multiphase cancellation

•

PC board layout noise immunity

•

Ease of use and design due to independent component

selection

•

Flexibility in operation for tailoring design to low cost or

high performance

START-UP SEQUENCE

During start-up, the number of operational phases and their

phase relationship is determined by the internal circuitry that

monitors the PWM outputs. Normally, the ADP3182 operates

as a 3-phase PWM controller. Grounding the PWM3 pin

programs 1/2-phase operation.

When the ADP3182 is enabled, the controller outputs a voltage

on PWM3 that is approximately 675 mV. An internal comparator

checks the pin’s voltage vs. a threshold of 300 mV. If the pin is

grounded, it is below the threshold and the phase is disabled.

The output resistance of the PWM pin is approximately 5 kΩ

during this detection time. Any external pull-down resistance

connected to the PWM pin should be more than 25 kΩ to

ensure proper operation. PWM1 and PWM2 are disabled

during the phase detection interval, which occurs during the

first two clock cycles of the internal oscillator. After this time, if

the PWM output is not grounded, the 5 kΩ resistance is

removed, and the PWM output switches between 0 V and 5 V. If

the PWM output is grounded, it remains off.

The PWM outputs are logic-level devices intended for driving

external gate drivers such as the ADP3418. Because each phase

is monitored independently, operation approaching 100% duty

cycle is possible. Also, more than one output can be on at the

same time for overlapping phases.

MASTER CLOCK FREQUENCY

The clock frequency of the ADP3182 is set with an external

resistor connected from the RT pin to ground. The frequency

follows the graph in Figure 4. To determine the frequency per

phase, the clock is divided by the number of phases in use. If

PWM3 is grounded, then divide the master clock by 2 for the

frequency of the remaining two phases.

It is important to note that if only one phase is used, the clock

will switch as if two phases were operating. This means that the

oscillator frequency must be set at twice the expected value to

program the desired PWM frequency.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3182 uses a differential-sensing, low offset voltage error

amplifier. This maintains a worst-case specification of ±2%

differential-sensing error over its full operating output voltage

and temperature range. The output voltage is sensed between

the FB and FBRTN pins. FB should be connected through a

resistor to the regulation point, usually the local bypass

capacitor for the load. FBRTN should be connected directly to

the remote sense ground point. The internal precision reference

is referenced to FBRTN, which has a minimal current of 100 µA

to allow accurate remote sensing. The internal error amplifier

compares the output of the reference to the FB pin to regulate

the output voltage.

OUTPUT CURRENT SENSING

The ADP3182 provides a dedicated current sense amplifier

(CSA) to monitor the total output current for current limit

detection. Sensing the load current at the output gives the total

average current being delivered to the load, which is an

inherently more accurate method than peak current detection

or sampling the current across a sense element such as the low-

side MOSFET. This amplifier can be configured several ways

depending on the objectives of the system:

•

Output inductor DCR sensing without a thermistor for

lowest cost

•

Output inductor DCR sensing with a thermistor for

improved accuracy for tracking inductor temperature

•

Sense resistors for highest accuracy measurements

The positive input of the CSA is connected to the CSREF pin,

which is connected to the output voltage. The inputs to the

amplifier are summed together through resistors from the

sensing element (such as the switch node side of the output

inductors) to the inverting input, CSSUM. The feedback resistor

between CSCOMP and CSSUM sets the gain of the amplifier,

and a filter capacitor is placed in parallel with this resistor. The

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