MCP2030 datasheet(38/66 Pages) MICROCHIP

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MCP2030

DS21981A-page 38

TABLE 5-1:

OUTPUT ENABLE FILTER

TIMING

TOEH is measured from the rising edge of the

demodulator output to the first falling edge. The pulse

width must fall within TOEH ≤ t ≤ TOET.

TOEL is measured from the falling edge of the

demodulator output to the rising edge of the next pulse.

The pulse width must fall within TOEL ≤ t ≤ TOET.

TOET is measured from rising edge to the next rising

edge (i.e., the sum of TOEH and TOEL). The sum of TOEH

and TOEL must be t ≤ TOET. If the Configuration Register

0 (Register 5-1), OEH<8:7> is set to ‘00’, then the filter

is disabled. See Figure 2-30 for this case.

The filter will reset, requiring a complete new successive

high and low period to enable LFDATA, under the

following conditions.

• The received high is not greater than the

configured minimum TOEH value.

• During TOEH, a loss of signal for longer than 56 μs

causes a filter Reset.

• The received low is not greater than the

configured minimum TOEL value.

• The received sequence exceeds the maximum

TOET value:

-TOEH + TOEL > TOET

-or TOEH > TOET

-or TOEL > TOET

• A Soft Reset SPI command is received.

If the filter resets due to a long high-time (TOEH > TOET),

the high-pulse timer will not begin timing again until

after a gap of TE and another low-to-high transition

occurs on the demodulator output.

Disabling the output enable filter disables the TOEH and

TOEL requirement and the device passes all detected

data. See Figure 2-30, Figure 2-31 and Figure 2-32 for

examples.

When viewed from an application perspective, from the

pin input, the actual output enable filter timing must

factor in the analog delays in the input path (such as

demodulator charge and discharge times).

•TOEH - TDR + TDF

•TOEL + TDR - TDF

The output enable filter starts immediately after TGAP,

the gap after AGC stabilization period.

5.16

Input Sensitivity Control

The device has typical input sensitivity of 3 mVPP. This

means any input signal with amplitude greater than 3

mVPP can be detected. The internal AGC loop regu-

lates the detecting signal amplitude when the input

level is greater than approximately 20 mVPP. This

signal amplitude is called “AGC-active level”. The AGC

loop regulates the input voltage so that the input signal

amplitude range will be kept within the linear range of

the detection circuits without saturation. The AGC

Active Status bit (AGCACT<5>) in STATUS Register 7

(Register 5-8) is set if the AGC loop regulates the input

voltage.

Table 5-2 shows the input sensitivity comparison when

the AGCSIG option is used. When AGCSIG option bit is

set, the demodulated output is available only when the

AGC loop is active (see Table 5-1). The channel input

sensitivity can be reduced by setting the appropriate

Configuration

registers.

Configuration

(Register 5-4), Configuration Register 4 (Register 5-5)

and Configuration Register 5 (Register 5-6) have the

option to reduce each channel gain from 0 dB to

approximately -30 dB.

OEH

<1:0>

OEL

<1:0>

TOEH

(ms)

TOEL

(ms)

TOET

(ms)

Filter Disabled

Note 1:

The timing values of TOEH and TOEL are

minimum and TOET is maximum at room

temperature and VDD = 3.0V, 32 kHz

oscillator.

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