MCP2030 datasheet(43/66 Pages) MICROCHIP

43 / 66 page

DS21981A-page 43

MCP2030

5.26

Factory Calibration

The device is calibrated during probe test to reduce the

device-to-device variation in standby current, internal

timing and sensitivity, as well as channel-to-channel

sensitivity variation.

5.27

De-Q’ing of Antenna Circuit

When the transponder is close to the base station, the

transponder coil may develop coil voltage higher than

VDE_Q. This condition is called “near field”. The device

detects the strong near field signal through the AGC

control, and de-Q’ing the antenna circuit to reduce the

input signal amplitude.

5.28

Demodulator

The demodulator recovers the modulation data from

the received signal, containing carrier plus data, by

appropriate envelope detection. The demodulator has

a fast rise (charge) time (TDR) and a fall time (TDF)

appropriate to an envelope of input signal (see

Section 1.0 “Electrical Specifications” for TDR and

TDF specifications). The demodulator contains the

full-wave rectifier, low-pass filter, peak detector and

data slicer.

FIGURE 5-6:

Demodulator Charge and Discharge.

5.29

Power-On Reset

This circuit remains in a Reset state until a sufficient

supply voltage is applied. The Reset releases when the

supply is sufficient for correct device operation,

nominally VPOR.

The Configuration registers are all cleared on a Power-

on Reset. As the Configuration registers are protected

by odd row and column parity, the ALERT pin will be

pulled down – indicating to the external microcontroller

section that the configuration memory is cleared and

requires new programming.

5.30

LFDATA Output Selection

The LFDATA output can be configured to pass the

Demodulator output, Received Signal Strength Indi-

cator (RSSI) output, or Carrier Clock (CCLK). See

Configuration Register 1 (Register 5-2) for more

details.

5.30.1

DEMODULATOR OUTPUT

The demodulator output is the default configuration of

the output selection. This is the output of an envelope

detection circuit. See Figure 5-6 for the demodulator

output.

For a clean data output or to save operating power, the

input channels can be individually enabled or disabled.

If more than one channel is enabled, the output is the

sum of each output of all enabled channels. There will

be no valid output if all three channels are disabled.

When the demodulated output is selected, the output is

available in two different conditions depending on how

the options of Configuration Register 0 (Register 5-1)

are set: Output Enable Filter is disabled or enabled.

See Section 2.0 “Typical Performance Curves” for

various demodulated data output.

Related Configuration register bits:

• Configuration Register 1 (Register 5-2),

DATOUT <8:7>:

bit 8 bit 7

: Demodulator Output

: Carrier Clock Output

: RSSI Output

• Configuration Register 0 (Register 5-1): all bits

Full-wave Rectifier output

Input at LC input pins

Demodulated LFDATA output

TDR

TDF

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