MCP2030 datasheet(44/66 Pages) MICROCHIP

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MCP2030

DS21981A-page 44

5.30.2

CARRIER CLOCK OUTPUT

When the carrier clock output is selected, the LFDATA

output is a square pulse of the input carrier clock and

available as soon as the AGC stabilization time (TAGC)

is completed. There are two Configuration register

options for the carrier clock output: (a) clock divide-by

one or (b) clock divide-by four, depending on bit

DATOUT<7> of Configuration Register 2 (Register 5-

3). The carrier clock output is available immediately

after the AGC settling time. The Output Enable Filter,

AGCSIG, and MODMIN options are applicable for the

carrier clock output in the same way as the demodu-

lated output. The input channel can be individually

enabled or disabled for the output. If more than one

channel is enabled, the output is the sum of each out-

put of all enabled channels. Therefore, the carrier clock

output waveform is not as precise as when only one

channel is enabled. It is recommended to enable one

channel only if a precise output waveform is desired.

There will be no valid output if all three channels are

disabled. See Figure 2-32 for carrier clock output

examples.

Related Configuration register bits:

• Configuration Register 1 (Register 5-2),

DATOUT <8:7>:

bit 8 bit 7

: Demodulator Output

: Carrier Clock Output

: RSSI Output

• Configuration Register 2 (Register 5-3),

CLKDIV<7>:

: Carrier Clock/1

: Carrier Clock/4

• Configuration Register 0 (Register 5-1): all bits

are affected

• Configuration Register 5 (Register 5-6)

5.30.3

RECEIVED SIGNAL STRENGTH

INDICATOR (RSSI) OUTPUT

An analog current output is available at the RSSI pin

when the Received Signal Strength Indicator (RSSI)

output is selected by the Configuration register. The

analog current is linearly proportional to the input signal

strength.

All timers in the circuit, such as inactivity timer, alarm

timer, and AGC initialization time, are disabled during

the RSSI mode. Therefore, the RSSI output is not

affected by the AGC stabilization time, and available

immediately when the RSSI option is selected. The

device enters Active mode immediately when the RSSI

output is selected.

When the device receives an SPI command during the

RSSI output, the RSSI mode is temporary disabled

until the SPI communication is completed. It returns to

the RSSI mode again after the SPI communication is

completed. The RSSI mode is held until another

output type is selected (CS low turns off the RSSI

signal). To obtain the RSSI output for a particular input

channel, or to save operating power, the input channel

can be individually enabled or disabled. If more than

one channel is enabled, the RSSI output is from the

strongest signal channel. There will be no valid output

if all three channels are disabled.

The RSSI output current is linearly proportional to the

input signal strength. There are variations between

channel to channel and device to device. See

Figure 2-13 for examples. The linearity (ILRRSSI) of

the RSSI output current is tested by sampling the

outputs for three input points: 37 mVPP, 100 mVPP,

and 370 mVPP. The RSSI output current for 100 mVPP

of input signal is compared with the expected output

current obtained from the line that is connecting the

two endpoints (37 mVPP and 370 mVPP). Equation 5-1

and Figure 5-7 show the details for the RSSI linearity

specification.

EQUATION 5-1:

RSSI LINEARITY

SPECIFICATION

FIGURE 5-7:

RSSI Linearity Test

Example.

ILRRSSI(%) =

Deviation at 100 mVPP of Input Signal

IRSSI for 370 mVPP of Input Signal

where,

Deviation at 100 mVPP of Input Signal =

[IRSSI measured - IRSSI expected] at 100 mVPP of input

signal.

IRSSI expected = RSSI current obtained from the line

that is connecting two endpoints (RSSI output currents

for 37 mVPP and 370 mVPP of inputs).

x 100%

37 mVPP

100 mVPP

370 mVPP

y = a+bx

= Measured

= Expected

d = Deviation

Input Signal Amplitude

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